diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl
index d8f98c8f69..1ef2f2b4bf 100644
--- a/flow/scripts/synth_preamble.tcl
+++ b/flow/scripts/synth_preamble.tcl
@@ -63,6 +63,16 @@ proc read_design_sources { } {
       lappend slang_args -G "$key=$value"
     }
 
+    # Automatically blackbox macros from ADDITIONAL_LIBS so that
+    # any competing Verilog definitions in the source files are
+    # ignored in favor of the liberty view, consistent with the
+    # behavior of the builtin Verilog frontend.
+    if { [env_var_exists_and_non_empty ADDITIONAL_LIBS] } {
+      foreach m [get_liberty_cell_names $::env(ADDITIONAL_LIBS)] {
+        lappend slang_args --blackboxed-module "$m"
+      }
+    }
+
     # Apply module blackboxing based on module names as they appear
     # in the input, that is before any module name mangling done
     # by elaboration and synthesis
diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl
index 04b4d3727e..deac8b6d0b 100644
--- a/flow/scripts/util.tcl
+++ b/flow/scripts/util.tcl
@@ -1,3 +1,18 @@
+# Extract cell names from liberty files by parsing "cell(...)" declarations
+proc get_liberty_cell_names { lib_files } {
+  set cell_names [list]
+  foreach lib $lib_files {
+    set fid [open $lib r]
+    while { [gets $fid line] >= 0 } {
+      if { [regexp {^\s*cell\s*\(\s*"?([^")\s]+)"?\s*\)} $line -> cell_name] } {
+        lappend cell_names $cell_name
+      }
+    }
+    close $fid
+  }
+  return $cell_names
+}
+
 proc log_cmd { cmd args } {
   # log the command, escape arguments with spaces
   set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" ;# tclint-disable-line line-length