diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 45208f8afe..012f81c8e0 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -99,4 +99,4 @@ "value": 7206, "compare": "<=" } -} +} \ No newline at end of file diff --git a/flow/designs/nangate45/ariane133/rules-base.json b/flow/designs/nangate45/ariane133/rules-base.json index 8e5071431f..6ad8080e09 100644 --- a/flow/designs/nangate45/ariane133/rules-base.json +++ b/flow/designs/nangate45/ariane133/rules-base.json @@ -99,4 +99,4 @@ "value": 840911, "compare": "<=" } -} +} \ No newline at end of file diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json index c4be1ed899..87db27968c 100644 --- a/flow/designs/nangate45/bp_fe_top/rules-base.json +++ b/flow/designs/nangate45/bp_fe_top/rules-base.json @@ -99,4 +99,4 @@ "value": 247483, "compare": "<=" } -} +} \ No newline at end of file diff --git a/flow/designs/nangate45/bp_multi_top/rules-base.json b/flow/designs/nangate45/bp_multi_top/rules-base.json index 763b6d62f4..56e5c9c67e 100644 --- a/flow/designs/nangate45/bp_multi_top/rules-base.json +++ b/flow/designs/nangate45/bp_multi_top/rules-base.json @@ -99,4 +99,4 @@ "value": 587157, "compare": "<=" } -} +} \ No newline at end of file diff --git a/flow/designs/nangate45/mempool_group/rules-base.json b/flow/designs/nangate45/mempool_group/rules-base.json index 48e089a5f2..aa57c0f78e 100644 --- a/flow/designs/nangate45/mempool_group/rules-base.json +++ b/flow/designs/nangate45/mempool_group/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 271098.37, + "value": 424000.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 295108, + "value": 451188, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 163160, + "value": 198708, "compare": "<=" }, "detailedplace__design__violations": { @@ -32,7 +32,7 @@ "compare": ">=" }, "cts__timing__setup__tns": { - "value": -10300.0, + "value": -11900.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -11100.0, + "value": -14200.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 4029078, + "value": 5795200, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 303227, + "value": 461696, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json index fcffced277..49b0eefcca 100644 --- a/flow/designs/nangate45/tinyRocket/rules-base.json +++ b/flow/designs/nangate45/tinyRocket/rules-base.json @@ -99,4 +99,4 @@ "value": 62486, "compare": "<=" } -} +} \ No newline at end of file diff --git a/flow/designs/sky130hd/chameleon/rules-base.json b/flow/designs/sky130hd/chameleon/rules-base.json index 6511dac5ba..3f105102ea 100644 --- a/flow/designs/sky130hd/chameleon/rules-base.json +++ b/flow/designs/sky130hd/chameleon/rules-base.json @@ -99,4 +99,4 @@ "value": 6493440, "compare": "<=" } -} +} \ No newline at end of file diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index d8f98c8f69..3edee2d454 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -63,6 +63,16 @@ proc read_design_sources { } { lappend slang_args -G "$key=$value" } + # Automatically blackbox macros from ADDITIONAL_LIBS so that + # any competing Verilog definitions in the source files are + # ignored in favor of the liberty view, consistent with the + # behavior of the builtin Verilog frontend. + if { [env_var_exists_and_non_empty ADDITIONAL_LIBS] } { + foreach m [get_liberty_cell_names] { + lappend slang_args --blackboxed-module "$m" + } + } + # Apply module blackboxing based on module names as they appear # in the input, that is before any module name mangling done # by elaboration and synthesis diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index af92dbe0c2..e309cedad3 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -1,3 +1,8 @@ +# Extract cell names +proc get_liberty_cell_names { } { + return [tee -q -s result.string select -list-mod =A:liberty_cell] +} + proc log_cmd { cmd args } { # log the command, escape arguments with spaces set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" ;# tclint-disable-line line-length