Record::instrument_seconds and PhaseLog::Instrument() are charged at five distinct sites in src/vllm/multimodal/render_phase_log.cpp: Open's pre-lock mutex wait (the entered clock read, the interval the row's ## Design 1 names as the reason the mechanism exists), Open's tail after SampleLocked, Close's tail, the sampler join, and SampleLocked's own self-charge. The suite reds only when EVERY site is removed at once.
Measured by mutation at the head of PR #1711, each mutation printing compile_status, git diff --numstat and the doctest test cases: / assertions: lines, with the tree restored byte-for-byte from a pristine copy and verified by sha256:
N6 — Open's pre-lock charge replaced by a (void) cast of the same expression, so the interval is computed and charged to nothing: test_render_phase_log GREEN, test cases: 1 | 1 passed | 0 failed | 4 skipped on each of the two cases run.
N4 — ChargeLocked's if (from < 0.0) return; becomes a clamp to zero, which the comment beside it argues at length is the defect that makes a gate pass: GREEN.
NNOSORT — ByStart stable-sorts an empty range, i.e. does not sort at all: GREEN. Every timeline this suite builds is already start-ordered, so the sort is a no-op on it. A REVERSED sort (NREVSORT) is red at CHECK(seconds >= 0.0) on -0.016996, so the order is held against inversion and not against removal.
R2 — ChargeLocked returns immediately, so nothing anywhere is charged: RED at REQUIRE(instrument > 0.0) in the render case.
N6's first staging is worth recording because it is the trap this project keeps hitting: written as if (false) { ... } it left entered unused and failed -Werror, compile_status=1. A mutation that fails to build reads exactly like a passing test, and only the printed compile status separated the two.
A per-site gate was written and run THREE times and it does not measure the site. The full account is kept in the comment where the case would have been, under WHY THERE IS NO PER-SITE CHARGE CASE HERE in tests/vllm/multimodal/test_render_phase_log.cpp. PhaseLog::Records() is the only public entry point that holds the process-wide mutex without charging itself, which is what makes it usable as a hold at all — and contention staged through it lands mostly in PhaseLog::Close's lock wait, which is charged to nobody (the sibling issue) and lies inside the CHILD's duration rather than in the parent's charge. The case passed in ISOLATION at a separation of 615x and failed 5 of 5 inside the suite: twice because no reader held the lock at all, and three times because a contended parent that took 21 ms was charged 112 us. A parent-against-parent comparison does not track the site under test however the contention is arranged.
NOT FIXED IN FLOW, deliberately. A flaky gate over an instrument whose entire subject is flaky gates is the failure this cluster exists to stop, and #1569 is the standing record of what an instrument whose own mutation cannot fail costs. What would settle it: a probe that holds the mutex through an entry point that does not charge itself AND lands the wait on the site under test, which needs Close to read a clock before its lock first — i.e. the sibling issue lands before this one can.
Owned by .agents/specs/ltx25-phase-instrument.md ## Owed.
Record::instrument_secondsandPhaseLog::Instrument()are charged at five distinct sites insrc/vllm/multimodal/render_phase_log.cpp:Open's pre-lock mutex wait (theenteredclock read, the interval the row's## Design1 names as the reason the mechanism exists),Open's tail afterSampleLocked,Close's tail, the sampler join, andSampleLocked's own self-charge. The suite reds only when EVERY site is removed at once.Measured by mutation at the head of PR #1711, each mutation printing
compile_status,git diff --numstatand the doctesttest cases:/assertions:lines, with the tree restored byte-for-byte from a pristine copy and verified by sha256:N6—Open's pre-lock charge replaced by a(void)cast of the same expression, so the interval is computed and charged to nothing:test_render_phase_logGREEN,test cases: 1 | 1 passed | 0 failed | 4 skippedon each of the two cases run.N4—ChargeLocked'sif (from < 0.0) return;becomes a clamp to zero, which the comment beside it argues at length is the defect that makes a gate pass: GREEN.NNOSORT—ByStartstable-sorts an empty range, i.e. does not sort at all: GREEN. Every timeline this suite builds is already start-ordered, so the sort is a no-op on it. A REVERSED sort (NREVSORT) is red atCHECK(seconds >= 0.0)on-0.016996, so the order is held against inversion and not against removal.R2—ChargeLockedreturns immediately, so nothing anywhere is charged: RED atREQUIRE(instrument > 0.0)in the render case.N6's first staging is worth recording because it is the trap this project keeps hitting: written asif (false) { ... }it leftenteredunused and failed-Werror,compile_status=1. A mutation that fails to build reads exactly like a passing test, and only the printed compile status separated the two.A per-site gate was written and run THREE times and it does not measure the site. The full account is kept in the comment where the case would have been, under
WHY THERE IS NO PER-SITE CHARGE CASE HEREintests/vllm/multimodal/test_render_phase_log.cpp.PhaseLog::Records()is the only public entry point that holds the process-wide mutex without charging itself, which is what makes it usable as a hold at all — and contention staged through it lands mostly inPhaseLog::Close's lock wait, which is charged to nobody (the sibling issue) and lies inside the CHILD's duration rather than in the parent's charge. The case passed in ISOLATION at a separation of 615x and failed 5 of 5 inside the suite: twice because no reader held the lock at all, and three times because a contended parent that took 21 ms was charged 112 us. A parent-against-parent comparison does not track the site under test however the contention is arranged.NOT FIXED IN FLOW, deliberately. A flaky gate over an instrument whose entire subject is flaky gates is the failure this cluster exists to stop, and #1569 is the standing record of what an instrument whose own mutation cannot fail costs. What would settle it: a probe that holds the mutex through an entry point that does not charge itself AND lands the wait on the site under test, which needs
Closeto read a clock before its lock first — i.e. the sibling issue lands before this one can.Owned by
.agents/specs/ltx25-phase-instrument.md## Owed.