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nrf_security: cracen_sw: Add config for ctr size workarounds
Add config for the workarounds required for socs which have a reduced ctr register size. Update existing workarounds to use this kconfig Signed-off-by: Dag Erik Gjørvad <[email protected]>
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7 files changed

+20
-17
lines changed

7 files changed

+20
-17
lines changed

‎subsys/nrf_security/cmake/psa_crypto_config.cmake‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -473,6 +473,7 @@ kconfig_check_and_set_base_to_one(PSA_NEED_CRACEN_TRNG_DRIVER)
473473
kconfig_check_and_set_base_to_one(PSA_CRYPTO_DRIVER_ALG_PRNG_TEST)
474474
kconfig_check_and_set_base_to_one(PSA_CRYPTO_DRIVER_IRONSIDE)
475475
kconfig_check_and_set_base_to_one(PSA_NEED_CRACEN_MULTIPART_WORKAROUNDS)
476+
kconfig_check_and_set_base_to_one(PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS)
476477
kconfig_check_and_set_base_to_one(PSA_NEED_CRACEN_IKG_INTERRUPT_WORKAROUND)
477478
kconfig_check_and_set_base_to_one(PSA_NEED_CRACEN_RNG_NO_ENTROPY_WORKAROUND)
478479
kconfig_check_and_set_base_to_one(PSA_NEED_CRACEN_ECC_KEY_GEN_PKE)

‎subsys/nrf_security/configs/psa_crypto_config.h.template‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -468,6 +468,7 @@
468468
#cmakedefine PSA_CRYPTO_DRIVER_ALG_PRNG_TEST @PSA_CRYPTO_DRIVER_ALG_PRNG_TEST@
469469
#cmakedefine PSA_CRYPTO_DRIVER_IRONSIDE @PSA_CRYPTO_DRIVER_IRONSIDE@
470470
#cmakedefine PSA_NEED_CRACEN_MULTIPART_WORKAROUNDS @PSA_NEED_CRACEN_MULTIPART_WORKAROUNDS@
471+
#cmakedefine PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS @PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS@
471472
#cmakedefine PSA_NEED_CRACEN_IKG_INTERRUPT_WORKAROUND @PSA_NEED_CRACEN_IKG_INTERRUPT_WORKAROUND@
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#cmakedefine PSA_NEED_CRACEN_RNG_NO_ENTROPY_WORKAROUND @PSA_NEED_CRACEN_RNG_NO_ENTROPY_WORKAROUND@
473474
#cmakedefine PSA_NEED_CRACEN_ECC_KEY_GEN_PKE @PSA_NEED_CRACEN_ECC_KEY_GEN_PKE@

‎subsys/nrf_security/src/drivers/cracen/CMakeLists.txt‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,7 @@ set(cracen_driver_sources)
1111
include(sxsymcrypt/sxsymcrypt.cmake)
1212
include(silexpk/silexpk.cmake)
1313
include(cracenpsa/cracenpsa.cmake)
14-
if(CONFIG_PSA_NEED_CRACEN_MULTIPART_WORKAROUNDS OR
15-
(CONFIG_SOC_NRF54LV10A AND CONFIG_PSA_NEED_CRACEN_CTR_AES))
14+
if(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS)
1615
include(cracen_sw/cracen_sw.cmake)
1716
endif()
1817

‎subsys/nrf_security/src/drivers/cracen/Kconfig‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,9 @@ config CRACEN_KMU_HW_PRESENT
1919
config PSA_NEED_CRACEN_MULTIPART_WORKAROUNDS
2020
def_bool SOC_NRF54LM20A
2121

22+
config PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS
23+
def_bool PSA_NEED_CRACEN_MULTIPART_WORKAROUNDS || SOC_NRF54LV10A
24+
2225
config PSA_NEED_CRACEN_IKG_INTERRUPT_WORKAROUND
2326
def_bool SOC_NRF54LM20A || SOC_NRF54LV10A || SOC_NRF7120_ENGA
2427

‎subsys/nrf_security/src/drivers/cracen/cracen_sw/cracen_sw.cmake‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,7 @@ if(CONFIG_PSA_NEED_CRACEN_MULTIPART_WORKAROUNDS AND CONFIG_PSA_NEED_CRACEN_MAC_D
3333
endif()
3434
endif()
3535

36-
if((CONFIG_PSA_NEED_CRACEN_MULTIPART_WORKAROUNDS OR CONFIG_SOC_NRF54LV10A) AND
37-
CONFIG_PSA_NEED_CRACEN_CTR_AES)
36+
if(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS AND CONFIG_PSA_NEED_CRACEN_CTR_AES)
3837
list(APPEND cracen_driver_sources
3938
${CMAKE_CURRENT_LIST_DIR}/src/cracen_sw_aes_ctr.c
4039
)

‎subsys/nrf_security/src/drivers/cracen/cracenpsa/include/cracen_psa_primitives.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -44,12 +44,12 @@
4444
#define CRACEN_MAX_CHACHA20_KEY_SIZE (32u)
4545

4646
/*
47-
* There is a HW limitation for nRF54LM20A and nRF54LV10A:
48-
* a maximum of 1 MB of plaintext or ciphertext is supported.
47+
* HW limitation for devices with smaller CTR size:
48+
* a maximum of 1 MB of plaintext or ciphertext is supported for CCM.
4949
*/
50-
#if defined(CONFIG_SOC_NRF54LM20A) || defined(CONFIG_SOC_NRF54LV10A)
50+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS)
5151
#define CRACEN_MAX_CCM_DATA_SIZE (65536U * SX_BLKCIPHER_AES_BLK_SZ)
52-
#endif /* CONFIG_SOC_NRF54LM20A || CONFIG_SOC_NRF54LV10A */
52+
#endif /* CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS */
5353

5454
/*
5555
* There are two key types supported for ciphers, CHACHA20 and AES,

‎subsys/nrf_security/src/drivers/cracen/cracenpsa/src/cipher.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323

2424
#include "cracen_psa_primitives.h"
2525

26-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
26+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
2727
#include <cracen_sw_aes_ctr.h>
2828
#endif
2929

@@ -288,7 +288,7 @@ psa_status_t cracen_cipher_encrypt(const psa_key_attributes_t *attributes,
288288
cracen_cipher_operation_t operation = {0};
289289
*output_length = 0;
290290

291-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
291+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
292292
/* Route AES_CTR to software implementation due to 16-bit counter limitation */
293293
if (alg == PSA_ALG_CTR) {
294294
if (output_size < input_length) {
@@ -364,7 +364,7 @@ psa_status_t cracen_cipher_decrypt(const psa_key_attributes_t *attributes,
364364
const size_t iv_size = (alg == PSA_ALG_STREAM_CIPHER) ? 12 : SX_BLKCIPHER_IV_SZ;
365365
*output_length = 0;
366366

367-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
367+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
368368
/* Route AES_CTR to software implementation due to 16-bit counter limitation */
369369
if (alg == PSA_ALG_CTR) {
370370
return cracen_sw_aes_ctr_crypt(attributes, key_buffer, key_buffer_size, input,
@@ -480,7 +480,7 @@ psa_status_t cracen_cipher_encrypt_setup(cracen_cipher_operation_t *operation,
480480
const uint8_t *key_buffer, size_t key_buffer_size,
481481
psa_algorithm_t alg)
482482
{
483-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
483+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
484484
/* Route AES_CTR to software implementation due to 16-bit counter limitation */
485485
if (alg == PSA_ALG_CTR) {
486486
return cracen_sw_aes_ctr_setup(operation, attributes, key_buffer, key_buffer_size);
@@ -496,7 +496,7 @@ psa_status_t cracen_cipher_decrypt_setup(cracen_cipher_operation_t *operation,
496496
psa_algorithm_t alg)
497497
{
498498

499-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
499+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
500500
/* Route AES_CTR to software implementation due to 16-bit counter limitation */
501501
if (alg == PSA_ALG_CTR) {
502502
return cracen_sw_aes_ctr_setup(operation, attributes, key_buffer, key_buffer_size);
@@ -511,7 +511,7 @@ psa_status_t cracen_cipher_set_iv(cracen_cipher_operation_t *operation, const ui
511511
{
512512
__ASSERT_NO_MSG(iv != NULL);
513513

514-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
514+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
515515
/* Route AES_CTR to software implementation due to 16-bit counter limitation */
516516
if (operation->alg == PSA_ALG_CTR) {
517517
return cracen_sw_aes_ctr_set_iv(operation, iv, iv_length);
@@ -554,7 +554,7 @@ psa_status_t cracen_cipher_update(cracen_cipher_operation_t *operation, const ui
554554
__ASSERT_NO_MSG(input != NULL || input_length == 0);
555555
__ASSERT_NO_MSG(output_length != NULL);
556556

557-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
557+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
558558
/* Route AES_CTR to software implementation due to 16-bit counter limitation */
559559
if (operation->alg == PSA_ALG_CTR) {
560560
return cracen_sw_aes_ctr_update(operation, input, input_length, output, output_size,
@@ -712,7 +712,7 @@ psa_status_t cracen_cipher_finish(cracen_cipher_operation_t *operation, uint8_t
712712
{
713713
__ASSERT_NO_MSG(output_length != NULL);
714714

715-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
715+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
716716
/* Route AES_CTR to software implementation due to 16-bit counter limitation */
717717
if (operation->alg == PSA_ALG_CTR) {
718718
return cracen_sw_aes_ctr_finish(operation, output_length);
@@ -859,7 +859,7 @@ psa_status_t cracen_cipher_finish(cracen_cipher_operation_t *operation, uint8_t
859859

860860
psa_status_t cracen_cipher_abort(cracen_cipher_operation_t *operation)
861861
{
862-
#if defined(CONFIG_SOC_NRF54LV10A) && defined(PSA_NEED_CRACEN_CTR_AES)
862+
#if defined(CONFIG_PSA_NEED_CRACEN_CTR_SIZE_WORKAROUNDS) && defined(PSA_NEED_CRACEN_CTR_AES)
863863
/* Route AES_CTR to software implementation due to 16-bit counter limitation */
864864
if (operation->alg == PSA_ALG_CTR) {
865865
/* Software AES CTR implementation doesn't allocate hardware resources to free */

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