Merge branch 'espressif:release/v5.5' into release/v5.5

Jason2866 · web-flow · commit 94803923cfae · 2025-09-03T17:12:28.000+02:00
diff --git a/.gitlab/ci/common.yml b/.gitlab/ci/common.yml
@@ -40,7 +40,7 @@ variables:
   GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags"
   # we're using .cache folder for caches
   GIT_CLEAN_FLAGS: -ffdx -e .cache/
-  LATEST_GIT_TAG: v5.5
+  LATEST_GIT_TAG: v5.5.1
 
   SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py"
   # by default we will fetch all submodules
diff --git a/README.md b/README.md
@@ -25,8 +25,8 @@ The following table shows ESP-IDF support of Espressif SoCs where ![alt text][pr
 |ESP32-C6     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_C6)           |
 |ESP32-H2     |![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_H2)           |
 |ESP32-P4     |                        |                        | ![alt text][supported] |  ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-P4)           |
-|ESP32-C5      |                        |                        |                        |               |![alt text][preview]   |[Announcement](https://www.espressif.com/en/news/ESP32-C5)           |
-|ESP32-C61     |                       |                        |                        |               |![alt text][preview]   |[Announcement](https://www.espressif.com/en/products/socs/esp32-c61) |
+|ESP32-C5      |                        |                        |                        |               |![alt text][supported]   |since v5.5.1, [Announcement](https://www.espressif.com/en/news/ESP32-C5)           |
+|ESP32-C61     |                       |                        |                        |               |![alt text][supported]   |since v5.5.1, [Announcement](https://www.espressif.com/en/products/socs/esp32-c61) |
 
 [supported]: https://img.shields.io/badge/-supported-green "supported"
 [preview]: https://img.shields.io/badge/-preview-orange "preview"
diff --git a/README_CN.md b/README_CN.md
@@ -25,8 +25,8 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux 
 |ESP32-C6     |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6)           |
 |ESP32-H2     |![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2)           |
 |ESP32-P4     |                         |                        | ![alt text][supported] | ![alt text][supported] |![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4)           |
-|ESP32-C5       |                        |                        |                   |                        |![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5)           |
-|ESP32-C61      |                       |                        |                    |                        |![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/products/socs/esp32-c61) |
+|ESP32-C5       |                        |                        |                   |                        |![alt text][supported] | 自 v5.5.1 开始，[芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5)           |
+|ESP32-C61      |                       |                        |                    |                        |![alt text][supported] | 自 v5.5.1 开始，[芯片发布公告](https://www.espressif.com/zh-hans/products/socs/esp32-c61) |
 
 
 [supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
diff --git a/components/esp_common/include/esp_idf_version.h b/components/esp_common/include/esp_idf_version.h
@@ -15,7 +15,7 @@ extern "C" {
 /** Minor version number (x.X.x) */
 #define ESP_IDF_VERSION_MINOR   5
 /** Patch version number (x.x.X) */
-#define ESP_IDF_VERSION_PATCH   0
+#define ESP_IDF_VERSION_PATCH   1
 
 /**
  * Macro to convert IDF version number into an integer
diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c
@@ -28,6 +28,10 @@ typedef enum {
     MODEM_CLOCK_MODEM_PRIVATE_FE,
     MODEM_CLOCK_COEXIST,
     MODEM_CLOCK_I2C_MASTER,
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+    MODEM_CLOCK_WIFI_APB,
+    MODEM_CLOCK_WIFI_BB_44M,
+#endif
 #if SOC_WIFI_SUPPORTED
     MODEM_CLOCK_WIFI_MAC,
     MODEM_CLOCK_WIFI_BB,
@@ -64,7 +68,9 @@ typedef struct modem_clock_context {
 static void IRAM_ATTR modem_clock_wifi_mac_configure(modem_clock_context_t *ctx, bool enable)
 {
     if (enable) {
+#if !SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
         modem_syscon_ll_enable_wifi_apb_clock(ctx->hal->syscon_dev, enable);
+#endif
         modem_syscon_ll_enable_wifi_mac_clock(ctx->hal->syscon_dev, enable);
     }
 }
@@ -86,6 +92,22 @@ static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx,
 }
 #endif // SOC_BT_SUPPORTED
 
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+static void IRAM_ATTR modem_clock_wifi_apb_configure(modem_clock_context_t *ctx, bool enable)
+{
+    if (enable) {
+        modem_syscon_ll_enable_wifi_apb_clock(ctx->hal->syscon_dev, enable);
+    }
+}
+
+static void IRAM_ATTR modem_clock_wifi_bb_44m_configure(modem_clock_context_t *ctx, bool enable)
+{
+    if (enable) {
+        modem_syscon_ll_enable_wifibb_44m_clock(ctx->hal->syscon_dev, enable);
+    }
+}
+#endif
+
 #if SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
 static void IRAM_ATTR modem_clock_ble_i154_bb_configure(modem_clock_context_t *ctx, bool enable)
 {
@@ -149,6 +171,10 @@ modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(voi
             [MODEM_CLOCK_MODEM_PRIVATE_FE]      = { .refs = 0, .configure = modem_clock_modem_private_fe_configure },
             [MODEM_CLOCK_COEXIST]               = { .refs = 0, .configure = modem_clock_coex_configure },
             [MODEM_CLOCK_I2C_MASTER]            = { .refs = 0, .configure = modem_clock_i2c_master_configure },
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+            [MODEM_CLOCK_WIFI_APB]              = { .refs = 0, .configure = modem_clock_wifi_apb_configure },
+            [MODEM_CLOCK_WIFI_BB_44M]           = { .refs = 0, .configure = modem_clock_wifi_bb_44m_configure },
+#endif
 #if SOC_WIFI_SUPPORTED
             [MODEM_CLOCK_WIFI_MAC]              = { .refs = 0, .configure = modem_clock_wifi_mac_configure },
             [MODEM_CLOCK_WIFI_BB]               = { .refs = 0, .configure = modem_clock_wifi_bb_configure },
@@ -273,15 +299,21 @@ void IRAM_ATTR modem_clock_module_mac_reset(periph_module_t module)
     }
     portEXIT_CRITICAL_SAFE(&ctx->lock);
 }
-
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+#define WIFI_CLOCK_DEPS         (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_WIFI_APB) | BIT(MODEM_CLOCK_WIFI_BB) | BIT(MODEM_CLOCK_WIFI_BB_44M) | BIT(MODEM_CLOCK_COEXIST))
+#else
 #define WIFI_CLOCK_DEPS         (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_WIFI_BB) | BIT(MODEM_CLOCK_COEXIST))
+#endif
 #define BLE_CLOCK_DEPS          (BIT(MODEM_CLOCK_BLE_MAC) | BIT(MODEM_CLOCK_BT_I154_COMMON_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST))
 #define IEEE802154_CLOCK_DEPS   (BIT(MODEM_CLOCK_802154_MAC) | BIT(MODEM_CLOCK_BT_I154_COMMON_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST))
 #define COEXIST_CLOCK_DEPS      (BIT(MODEM_CLOCK_COEXIST))
 #define PHY_CLOCK_DEPS          (BIT(MODEM_CLOCK_I2C_MASTER) | BIT(MODEM_CLOCK_MODEM_ADC_COMMON_FE) | BIT(MODEM_CLOCK_MODEM_PRIVATE_FE))
 #define I2C_ANA_MST_CLOCK_DEPS  (BIT(MODEM_CLOCK_I2C_MASTER))
 #define MODEM_ETM_CLOCK_DEPS    (BIT(MODEM_CLOCK_ETM))
 #define MODEM_ADC_COMMON_FE_CLOCK_DEPS  (BIT(MODEM_CLOCK_MODEM_ADC_COMMON_FE))
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+#define PHY_CALIBRATION_CLOCK_DEPS      (BIT(MODEM_CLOCK_WIFI_APB) | BIT(MODEM_CLOCK_WIFI_BB_44M))
+#endif
 
 static IRAM_ATTR uint32_t modem_clock_get_module_deps(periph_module_t module)
 {
@@ -299,6 +331,9 @@ static IRAM_ATTR uint32_t modem_clock_get_module_deps(periph_module_t module)
 #if SOC_BT_SUPPORTED
         case PERIPH_BT_MODULE:                  deps = BLE_CLOCK_DEPS;                  break;
 #endif
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+        case PERIPH_PHY_CALIBRATION_MODULE:     deps = PHY_CALIBRATION_CLOCK_DEPS;      break;
+#endif
 #if SOC_IEEE802154_SUPPORTED
         case PERIPH_IEEE802154_MODULE:          deps = IEEE802154_CLOCK_DEPS;           break;
 #endif
diff --git a/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
@@ -486,7 +486,7 @@ typedef struct pmu_sleep_machine_constant {
         .power_supply_wait_time_us      = 20,   \
         .power_up_wait_time_us          = 2,    \
         .regdma_s2m_work_time_us        = 270,  \
-        .regdma_s2a_work_time_us        = 666,  \
+        .regdma_s2a_work_time_us        = 800,  \
         .regdma_m2a_work_time_us        = 296,  \
         .regdma_a2s_work_time_us        = 586,  \
         .regdma_rf_on_work_time_us      = 138,  \
diff --git a/components/esp_phy/lib b/components/esp_phy/lib
@@ -1 +1 @@
-Subproject commit b942b97a65e92b5899636f2dc40e8336d43ee107
+Subproject commit 45ce2703403784b4c3983a52e453988d61eb0e9d
diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c
@@ -49,6 +49,10 @@
 #include "esp_private/sleep_modem.h"
 #endif
 #include "hal/efuse_hal.h"
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+#include "esp_private/esp_modem_clock.h"
+#include "soc/periph_defs.h"
+#endif
 
 #if CONFIG_IDF_TARGET_ESP32
 extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb;
@@ -268,6 +272,22 @@ IRAM_ATTR void esp_phy_common_clock_disable(void)
     wifi_bt_common_module_disable();
 }
 
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+IRAM_ATTR void esp_phy_calibration_clock_enable(esp_phy_modem_t modem)
+{
+    if (modem == PHY_MODEM_BT || modem == PHY_MODEM_IEEE802154) {
+        modem_clock_module_enable(PERIPH_PHY_CALIBRATION_MODULE);
+    }
+}
+
+IRAM_ATTR void esp_phy_calibration_clock_disable(esp_phy_modem_t modem)
+{
+    if (modem == PHY_MODEM_BT || modem == PHY_MODEM_IEEE802154) {
+        modem_clock_module_disable(PERIPH_PHY_CALIBRATION_MODULE);
+    }
+}
+#endif
+
 #if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
 static inline void phy_digital_regs_store(void)
 {
@@ -296,6 +316,9 @@ void esp_phy_enable(esp_phy_modem_t modem)
         phy_update_wifi_mac_time(false, s_phy_rf_en_ts);
 #endif
         esp_phy_common_clock_enable();
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+        esp_phy_calibration_clock_enable(modem);
+#endif
         if (s_is_phy_calibrated == false) {
             esp_phy_load_cal_and_init();
             s_is_phy_calibrated = true;
@@ -337,7 +360,9 @@ void esp_phy_enable(esp_phy_modem_t modem)
             phy_ant_update();
             phy_ant_clr_update_flag();
         }
-
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+        esp_phy_calibration_clock_disable(modem);
+#endif
     }
     phy_set_modem_flag(modem);
 #if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_ESP_PHY_DISABLE_PLL_TRACK
diff --git a/components/esp_psram/device/esp_psram_impl_ap_hex.c b/components/esp_psram/device/esp_psram_impl_ap_hex.c
@@ -391,8 +391,6 @@ static void s_configure_psram_ecc(void)
 {
     psram_ctrlr_ll_enable_16to18_ecc(PSRAM_CTRLR_LL_MSPI_ID_2, true);
     psram_ctrlr_ll_enable_skip_page_corner(PSRAM_CTRLR_LL_MSPI_ID_2, true);
-    psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_2, true);
-    psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_2, 2048);
     psram_ctrlr_ll_enable_ecc_addr_conversion(PSRAM_CTRLR_LL_MSPI_ID_2, 2048);
 
     /**
@@ -427,6 +425,8 @@ esp_err_t esp_psram_impl_enable(void)
     mspi_timing_ll_enable_dqs(true);
 
     s_set_psram_cs_timing();
+    psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_2, true);
+    psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_2, 2048);
 #if CONFIG_SPIRAM_ECC_ENABLE
     s_configure_psram_ecc();
 #endif
diff --git a/components/esp_psram/device/esp_psram_impl_ap_quad.c b/components/esp_psram/device/esp_psram_impl_ap_quad.c
@@ -234,8 +234,6 @@ static void s_configure_psram_ecc(void)
 {
     psram_ctrlr_ll_set_ecc_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_ECC_MODE_16TO18);
     psram_ctrlr_ll_enable_skip_page_corner(PSRAM_CTRLR_LL_MSPI_ID_0, true);
-    psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_0, true);
-    psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_PAGE_SIZE);
     psram_ctrlr_ll_enable_ecc_addr_conversion(PSRAM_CTRLR_LL_MSPI_ID_0, true);
 
     /**
@@ -399,6 +397,15 @@ esp_err_t esp_psram_impl_enable(void)
     psram_reset_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
     //SPI1: send QPI enable command
     psram_enable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
+    //MSPI cross page configs
+    uint32_t page_size = 0;
+    if (s_psram_size == PSRAM_SIZE_2MB) {
+        page_size = 512;
+    } else {
+        page_size = 1024;
+    }
+    psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_1, true);
+    psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_1, page_size);
 
 #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
     //Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
diff --git a/components/esp_psram/device/esp_quad_psram_defs_ap.h b/components/esp_psram/device/esp_quad_psram_defs_ap.h
@@ -78,7 +78,6 @@ extern "C" {
 #define PSRAM_QUAD_CS_SETUP_VAL           1
 #define PSRAM_QUAD_CS_ECC_HOLD_TIME_VAL   3
 
-#define PSRAM_QUAD_PAGE_SIZE              512
 #define PSRAM_QUAD_ECC_ENABLE_MASK        BIT(8)
 
 // QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these.
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
@@ -40,7 +40,7 @@ ieee80211_ampdu_start_age_timer = 0x40000b5c;
 ieee80211_is_tx_allowed = 0x40000b64;
 ieee80211_output_pending_eb = 0x40000b68;
 ieee80211_output_process = 0x40000b6c;
-ieee80211_set_tx_desc = 0x40000b70;
+/*ieee80211_set_tx_desc = 0x40000b70;*/
 ieee80211_classify = 0x40000b74;
 ieee80211_copy_eb_header = 0x40000b78;
 ieee80211_recycle_cache_eb = 0x40000b7c;
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
@@ -36,7 +36,7 @@ ieee80211_ampdu_start_age_timer = 0x40000ac4;
 ieee80211_is_tx_allowed = 0x40000acc;
 ieee80211_output_pending_eb = 0x40000ad0;
 ieee80211_output_process = 0x40000ad4;
-ieee80211_set_tx_desc = 0x40000ad8;
+/*ieee80211_set_tx_desc = 0x40000ad8;*/
 ieee80211_classify = 0x40000adc;
 ieee80211_copy_eb_header = 0x40000ae0;
 ieee80211_recycle_cache_eb = 0x40000ae4;
diff --git a/components/esp_rom/test_esp_rom.py b/components/esp_rom/test_esp_rom.py
@@ -27,6 +27,9 @@ def test_roms_check_supported_chips() -> None:
     with open(ROMS_JSON, 'r') as f:
         roms_json = json.load(f)
     for chip in SUPPORTED_TARGETS:
+        if chip in ['esp32c5', 'esp32c61']:
+            # IDFCI-3109
+            continue
         assert chip in roms_json, f'Have no ROM data for chip {chip}'
 
 
diff --git a/components/hal/esp32c5/include/hal/modem_syscon_ll.h b/components/hal/esp32c5/include/hal/modem_syscon_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -327,12 +327,23 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
 __attribute__((always_inline))
 static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en)
 {
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+    /* Configure
+        clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_80m
+        clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1
+        clk_wifibb_160x1
+
+        clk_wifibb_44m is configured in modem_syscon_ll_enable_wifibb_44m_clock
+    */
+    modem_syscon_ll_clk_conf1_configure(hw, en, 0x1fb);
+#else
     /* Configure
         clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_44m / clk_wifibb_80m
         clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1
         clk_wifibb_160x1
     */
     modem_syscon_ll_clk_conf1_configure(hw, en, 0x1ff);
+#endif
 }
 
 __attribute__((always_inline))
diff --git a/components/hal/esp32c61/include/hal/modem_syscon_ll.h b/components/hal/esp32c61/include/hal/modem_syscon_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -327,12 +327,23 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
 __attribute__((always_inline))
 static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en)
 {
+#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+    /* Configure
+        clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_80m
+        clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1
+        clk_wifibb_160x1
+
+        clk_wifibb_44m is configured in modem_syscon_ll_enable_wifibb_44m_clock
+    */
+    modem_syscon_ll_clk_conf1_configure(hw, en, 0x1fb);
+#else
     /* Configure
         clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_44m / clk_wifibb_80m
         clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1
         clk_wifibb_160x1
     */
     modem_syscon_ll_clk_conf1_configure(hw, en, 0x1ff);
+#endif
 }
 
 __attribute__((always_inline))
diff --git a/components/hal/esp32s3/include/hal/psram_ctrlr_ll.h b/components/hal/esp32s3/include/hal/psram_ctrlr_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -226,6 +226,30 @@ static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena
     SPIMEM1.ctrl.fcmd_quad = ena;
 }
 
+/**
+ * @brief Set page size
+ *
+ * @param mspi_id      mspi_id
+ * @param size         page size
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_set_page_size(uint32_t mspi_id, uint32_t size)
+{
+    //for compatibility
+}
+
+/**
+ * @brief Enable splitting transactions
+ *
+ * @param mspi_id      mspi_id
+ * @param en           enable / disable
+ */
+__attribute__((always_inline))
+static inline void psram_ctrlr_ll_enable_split_trans(uint32_t mspi_id, bool en)
+{
+    //for compatibility
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -1859,6 +1859,10 @@ config SOC_BLE_CTE_SUPPORTED
     bool
     default y
 
+config SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
+    bool
+    default y
+
 config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR
     bool
     default y
diff --git a/components/soc/esp32c5/include/soc/periph_defs.h b/components/soc/esp32c5/include/soc/periph_defs.h
@@ -73,12 +73,13 @@ typedef enum {
     PERIPH_ANA_I2C_MASTER_MODULE,
     PERIPH_MODEM_ETM_MODULE,
     PERIPH_MODEM_ADC_COMMON_FE_MODULE,
+    PERIPH_PHY_CALIBRATION_MODULE,
     PERIPH_MODULE_MAX
     /*  !!! Don't append soc modules here !!! */
 } periph_module_t;
 
 #define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
-#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
+#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_CALIBRATION_MODULE
 #define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
 #define IS_MODEM_MODULE(periph)  ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))
 
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
diff --git a/components/soc/esp32c61/include/soc/periph_defs.h b/components/soc/esp32c61/include/soc/periph_defs.h
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
diff --git a/examples/protocols/mqtt/ssl_psk/sdkconfig.defaults b/examples/protocols/mqtt/ssl_psk/sdkconfig.defaults
diff --git a/examples/protocols/mqtt5/sdkconfig.defaults b/examples/protocols/mqtt5/sdkconfig.defaults
diff --git a/tools/cmake/version.cmake b/tools/cmake/version.cmake
diff --git a/tools/idf_py_actions/constants.py b/tools/idf_py_actions/constants.py
