diff --git a/aarch32-cpu/Cargo.toml b/aarch32-cpu/Cargo.toml
index 76903a97..b0a9d72c 100644
--- a/aarch32-cpu/Cargo.toml
+++ b/aarch32-cpu/Cargo.toml
@@ -51,11 +51,25 @@ serde = ["dep:serde", "arbitrary-int/serde"]
 check-asm = []
 
 [package.metadata.docs.rs]
-# This is a list of supported Tier 2 targets, as of latest stable
 targets = [
-    "armv7r-none-eabihf",
-    "armv7r-none-eabi",
-    "armv7a-none-eabihf",
+    "armebv7r-none-eabi",
+    "armebv7r-none-eabihf",
+    "armv4t-none-eabi",
+    "armv5te-none-eabi",
+    "armv6-none-eabi",
+    "armv6-none-eabihf",
     "armv7a-none-eabi",
-    "armv8r-none-eabihf"
+    "armv7a-none-eabihf",
+    "armv7r-none-eabi",
+    "armv7r-none-eabihf",
+    "armv8r-none-eabihf",
+    "thumbv4t-none-eabi",
+    "thumbv5te-none-eabi",
+    "thumbv6-none-eabi",
+    "thumbv7a-none-eabi",
+    "thumbv7a-none-eabihf",
+    "thumbv7r-none-eabi",
+    "thumbv7r-none-eabihf",
+    "thumbv8r-none-eabihf",
 ]
+cargo-args = ["-Z", "build-std"]
diff --git a/aarch32-cpu/src/asmv4.rs b/aarch32-cpu/src/asmv4.rs
index 4b0df97e..3dada594 100644
--- a/aarch32-cpu/src/asmv4.rs
+++ b/aarch32-cpu/src/asmv4.rs
@@ -109,11 +109,3 @@ pub fn core_id() -> u32 {
     }
     r & 0x00FF_FFFF
 }
-
-#[no_mangle]
-pub extern "C" fn __sync_synchronize() {
-    // we don't have a barrier instruction - the linux kernel just uses an empty inline asm block
-    unsafe {
-        core::arch::asm!("");
-    }
-}
diff --git a/aarch32-cpu/src/generic_timer/el0.rs b/aarch32-cpu/src/generic_timer/el0.rs
index d4a571e6..90dd61f3 100644
--- a/aarch32-cpu/src/generic_timer/el0.rs
+++ b/aarch32-cpu/src/generic_timer/el0.rs
@@ -2,7 +2,7 @@
 
 use crate::register;
 
-/// Represents our Physical Timer when we are running at EL0.
+/// Represents our Generic Physical Timer when we are running at EL0.
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
@@ -75,11 +75,11 @@ impl super::GenericTimer for El0PhysicalTimer {
     }
 }
 
-/// Represents our Virtual Timer when we are running at EL0.
+/// Represents our Generic Virtual Timer when we are running at EL0.
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
-/// [El1PhysicalTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
+/// [El1VirtualTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
 pub struct El0VirtualTimer();
 
 impl El0VirtualTimer {
diff --git a/aarch32-cpu/src/lib.rs b/aarch32-cpu/src/lib.rs
index 4df0fce5..3db2b991 100644
--- a/aarch32-cpu/src/lib.rs
+++ b/aarch32-cpu/src/lib.rs
@@ -1,7 +1,14 @@
 //! CPU/peripheral support for Arm AArch32
 #![no_std]
+#![deny(missing_docs)]
+#![deny(unsafe_op_in_unsafe_fn)]
+#![deny(clippy::missing_safety_doc)]
+#![deny(clippy::unnecessary_safety_comment)]
+#![deny(clippy::unnecessary_safety_doc)]
 
-mod critical_section;
+pub mod cache;
+pub mod interrupt;
+pub mod register;
 
 #[cfg(any(
     doc,
@@ -21,26 +28,22 @@ pub mod asm;
 #[path = "asmv4.rs"]
 pub mod asm;
 
-pub mod cache;
-
 #[cfg(any(test, doc, arm_architecture = "v7-a", arm_architecture = "v8-r"))]
 pub mod generic_timer;
 
-pub mod interrupt;
-
-#[cfg(any(test, doc, arm_architecture = "v7-a"))]
+#[cfg(any(test, arm_profile = "a", arm_profile = "legacy"))]
 pub mod mmu;
 
-pub mod register;
+#[cfg(any(test, arm_architecture = "v7-r"))]
+pub mod pmsav7;
+
+#[cfg(any(test, arm_architecture = "v8-r"))]
+pub mod pmsav8;
 
 #[cfg(target_arch = "arm")]
 pub mod stacks;
 
-#[cfg(any(test, doc, arm_architecture = "v7-r"))]
-pub mod pmsav7;
-
-#[cfg(any(test, doc, arm_architecture = "v8-r"))]
-pub mod pmsav8;
+mod critical_section;
 
 /// Generate an SVC call with no parameters.
 ///
diff --git a/aarch32-cpu/src/mmu.rs b/aarch32-cpu/src/mmu.rs
index baafeacc..2763b5d9 100644
--- a/aarch32-cpu/src/mmu.rs
+++ b/aarch32-cpu/src/mmu.rs
@@ -9,7 +9,11 @@ pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
 ///
 /// You should create a static variable of this type, to represent your page table.
 #[repr(C, align(1048576))]
+#[derive(Debug)]
 pub struct L1Table {
+    /// Our mutable list of MMU table entries
+    ///
+    /// This table is read by the hardware.
     pub entries: core::cell::UnsafeCell<[L1Section; NUM_L1_PAGE_TABLE_ENTRIES]>,
 }
 
@@ -24,25 +28,39 @@ unsafe impl Sync for L1Table {}
 pub struct InvalidL1EntryType(pub L1EntryType);
 
 /// Access permissions for a region of memory
-#[bitbybit::bitenum(u3, exhaustive = true)]
+#[bitbybit::bitenum(u3)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
 pub enum AccessPermissions {
+    /// All accesses generate Permission faults
     PermissionFault = 0b000,
+    /// Privileged access only
     PrivilegedOnly = 0b001,
+    /// Writes in User mode generate Permission faults
     NoUserWrite = 0b010,
+    /// Full access
     FullAccess = 0b011,
-    _Reserved1 = 0b100,
+    /// Privileged read-only
     PrivilegedReadOnly = 0b101,
-    ReadOnly = 0b110,
-    _Reserved2 = 0b111,
+    /// Privileged and User read-only (deprecated in VMSAv7)
+    ReadOnlyv6 = 0b110,
+    /// Privileged and User read-only
+    ReadOnly = 0b111,
 }
 
 impl AccessPermissions {
+    /// Create a new [`AccessPermissions`] value from the APX bit at the AP bit
+    /// pair
+    ///
+    /// Will panic if you select an invalid value.
     #[inline]
     pub const fn new(apx: bool, ap: u2) -> Self {
-        Self::new_with_raw_value(u3::new(((apx as u8) << 2) | ap.value()))
+        let x = u3::new(((apx as u8) << 2) | ap.value());
+        let Ok(ap) = Self::new_with_raw_value(x) else {
+            panic!("Invalid access permissions");
+        };
+        ap
     }
 
     /// AP bit for the given access permission.
@@ -65,21 +83,25 @@ impl AccessPermissions {
 #[derive(Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum L1EntryType {
-    /// Access generates an abort exception. Indicates an unmapped virtual address.
+    /// Access generates an abort exception. Indicates an unmapped virtual
+    /// address.
     Fault = 0b00,
-    /// Entry points to a L2 translation table, allowing 1 MB of memory to be further divided
+    /// Entry points to a L2 translation table, allowing 1 MB of memory to be
+    /// further divided
     PageTable = 0b01,
     /// Maps a 1 MB region to a physical address.
     Section = 0b10,
-    /// Special 1MB section entry which requires 16 entries in the translation table.
+    /// Special 1MB section entry which requires 16 entries in the translation
+    /// table.
     Supersection = 0b11,
 }
 
-/// The ARM Cortex-A architecture reference manual p.1363 specifies these attributes in more detail.
+/// The ARM Cortex-A architecture reference manual p.1363 specifies these
+/// attributes in more detail.
 ///
-/// The B (Bufferable), C (Cacheable), and TEX (Type extension) bit names are inherited from
-/// earlier versions of the architecture. These names no longer adequately describe the function
-/// of the B, C, and TEX bits.
+/// The B (Bufferable), C (Cacheable), and TEX (Type extension) bit names are
+/// inherited from earlier versions of the architecture. These names no longer
+/// adequately describe the function of the B, C, and TEX bits.
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -91,6 +113,7 @@ pub struct MemoryRegionAttributesRaw {
 }
 
 impl MemoryRegionAttributesRaw {
+    /// Create a new [`MemoryRegionAttributesRaw`] from constituent parts
     #[inline]
     pub const fn new(type_extensions: u3, c: bool, b: bool) -> Self {
         Self {
@@ -105,11 +128,15 @@ impl MemoryRegionAttributesRaw {
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
-#[derive(Debug)]
-pub enum CacheableMemoryAttribute {
+#[derive(Debug, PartialEq, Eq)]
+pub enum CachePolicy {
+    /// Non-cacheable
     NonCacheable = 0b00,
+    /// Write-Back Cacheable, Write-Allocate
     WriteBackWriteAlloc = 0b01,
+    /// Write-Through Cacheable
     WriteThroughNoWriteAlloc = 0b10,
+    /// Write-Back Cacheable, no Write-Allocate
     WriteBackNoWriteAlloc = 0b11,
 }
 
@@ -118,20 +145,43 @@ pub enum CacheableMemoryAttribute {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub enum MemoryRegionAttributes {
+    /// Strongly- ordered
+    ///
+    /// All memory accesses to Strongly-ordered memory occur in program order.
+    /// All Strongly-ordered regions are assumed to be Shareable.
     StronglyOrdered,
+    /// Device Shareable
+    ///
+    /// Intended to handle memory-mapped peripherals that are shared by several
+    /// processors.
     ShareableDevice,
+    /// Normal Memory, Write-Through Cacheable for both Inner and Outer Cache
     OuterAndInnerWriteThroughNoWriteAlloc,
+    /// Normal Memory, Write-Back no Write-Allocate Cacheable for both Inner and
+    /// Outer Cache
     OuterAndInnerWriteBackNoWriteAlloc,
+    /// Normal Memory, Non-cacheable for both Inner and Outer Cache
     OuterAndInnerNonCacheable,
+    /// Normal Memory, Write-Back Write-Allocate Cacheable for both Inner and
+    /// Outer Cache
     OuterAndInnerWriteBackWriteAlloc,
+    /// Device Non-Shareable
+    ///
+    /// Intended to handle memory-mapped peripherals that are used only by a
+    /// single processor.
     NonShareableDevice,
+    /// Normal Memory, where Inner and Outer cache have different settings
     CacheableMemory {
-        inner: CacheableMemoryAttribute,
-        outer: CacheableMemoryAttribute,
+        /// Settings for the Inner Cache
+        inner: CachePolicy,
+        /// Settings for the Outer Cache
+        outer: CachePolicy,
     },
 }
 
 impl MemoryRegionAttributes {
+    /// Convert the Rust enum type [`MemoryRegionAttributes`] into a raw
+    /// [`MemoryRegionAttributesRaw`] value for the hardware
     pub const fn as_raw(&self) -> MemoryRegionAttributesRaw {
         match self {
             MemoryRegionAttributes::StronglyOrdered => {
@@ -175,10 +225,13 @@ pub struct SectionAttributes {
     pub non_global: bool,
     /// Implementation defined bit.
     pub p_bit: bool,
+    /// Is memory shareable across multiple CPUs
     pub shareable: bool,
-    /// AP bits
+    /// Access permissions
     pub access: AccessPermissions,
+    /// Raw memory attributes
     pub memory_attrs: MemoryRegionAttributesRaw,
+    /// Domain value for this section
     pub domain: u4,
     /// xN bit.
     pub execute_never: bool,
@@ -195,7 +248,8 @@ impl SectionAttributes {
         Ok(Self::from_raw_unchecked(raw))
     }
 
-    /// Retrieves the corresponding L1 section part without the section base address being set.
+    /// Retrieves the corresponding L1 section part without the section base
+    /// address being set.
     const fn l1_section_part(&self) -> L1Section {
         L1Section::builder()
             .with_base_addr_upper_bits(u12::new(0))
@@ -231,8 +285,9 @@ impl SectionAttributes {
 
 /// 1 MB section translation entry, mapping a 1 MB region to a physical address.
 ///
-/// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) or the ARMv7-A and ArmV7-R
-/// architecture reference manual p.1323 specify these attributes in more detail.
+/// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) or the
+/// ARMv7-A and ArmV7-R architecture reference manual p.1323 specify these
+/// attributes in more detail.
 #[bitbybit::bitfield(u32, default = 0, defmt_fields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(PartialEq, Eq)]
@@ -246,23 +301,31 @@ pub struct L1Section {
     /// Shareable bit.
     #[bit(16, rw)]
     s: bool,
+    /// Part of the access permissions field
     #[bit(15, rw)]
     apx: bool,
-    /// Type extension bits.
+    /// Memory Region Attribute bit
     #[bits(12..=14, rw)]
     tex: u3,
+    /// Part of the access permissions field
     #[bits(10..=11, rw)]
     ap: u2,
+    /// Implementation defined bit
     #[bit(9, rw)]
     p_bit: bool,
+    /// Domain field
     #[bits(5..=8, rw)]
     domain: u4,
+    /// Execute-never bit
     #[bit(4, rw)]
     xn: bool,
+    /// Memory Region Attribute bit
     #[bit(3, rw)]
     c: bool,
+    /// Memory Region Attribute bit
     #[bit(2, rw)]
     b: bool,
+    /// Entry Type
     #[bits(0..=1, rw)]
     entry_type: L1EntryType,
 }
@@ -287,11 +350,12 @@ impl core::fmt::Debug for L1Section {
 }
 
 impl L1Section {
-    /// Generates a new L1 section from a physical address and section attributes.
+    /// Generates a new L1 section from a physical address and section
+    /// attributes.
     ///
-    /// The uppermost 12 bits of the physical address define which 1 MB of virtual address space
-    /// are being accessed. They will be stored in the L1 section table. This address MUST be
-    /// aligned to 1 MB.
+    /// The uppermost 12 bits of the physical address define which 1 MB of
+    /// virtual address space are being accessed. They will be stored in the L1
+    /// section table. This address MUST be aligned to 1 MB.
     ///
     /// # Panics
     ///
@@ -316,7 +380,8 @@ impl L1Section {
         *self = Self::new_with_addr_upper_bits_and_attrs(self.base_addr_upper_bits(), section_attrs)
     }
 
-    /// Create a new L1 section with the given upper 12 bits of the address and section attributes.
+    /// Create a new L1 section with the given upper 12 bits of the address and
+    /// section attributes.
     #[inline]
     pub const fn new_with_addr_upper_bits_and_attrs(
         addr_upper_twelve_bits: u12,
@@ -368,8 +433,8 @@ mod tests {
         access: AccessPermissions::FullAccess,
         // TEX 0b101, c false, b true
         memory_attrs: MemoryRegionAttributes::CacheableMemory {
-            inner: CacheableMemoryAttribute::WriteBackWriteAlloc,
-            outer: CacheableMemoryAttribute::WriteBackWriteAlloc,
+            inner: CachePolicy::WriteBackWriteAlloc,
+            outer: CachePolicy::WriteBackWriteAlloc,
         }
         .as_raw(),
         domain: u4::new(0b1010),
@@ -431,7 +496,7 @@ mod tests {
             p_bit: true,
             shareable: false,
             // APX true, AP 0b10
-            access: AccessPermissions::ReadOnly,
+            access: AccessPermissions::ReadOnlyv6,
             // TEX 0b000, c false, b false
             memory_attrs: MemoryRegionAttributes::StronglyOrdered.as_raw(),
             domain: u4::new(0b1001),
diff --git a/aarch32-cpu/src/pmsav7.rs b/aarch32-cpu/src/pmsav7.rs
index 2b55a457..9706d3e2 100644
--- a/aarch32-cpu/src/pmsav7.rs
+++ b/aarch32-cpu/src/pmsav7.rs
@@ -8,6 +8,7 @@
 use crate::register;
 
 use arbitrary_int::{u2, u3};
+
 #[doc(inline)]
 pub use register::drsr::RegionSize;
 
@@ -235,21 +236,42 @@ pub enum MemAttr {
     /// Strongly-ordered memory
     StronglyOrdered,
     /// Device (shareable or non-shareable)
-    Device { shareable: bool },
-    /// Outer and Inner Write-Through, no Write-Allocate
-    WriteThroughNoWriteAllocate { shareable: bool },
-    /// Outer and Inner Write-Back, no Write-Allocate
-    WriteBackNoWriteAllocate { shareable: bool },
-    /// Outer and Inner Non-cacheable
-    NonCacheable { shareable: bool },
+    Device {
+        /// Is device shareable (across multiple CPUs)
+        shareable: bool,
+    },
+    /// Normal Memory, Outer and Inner Cache are Write-Through, no Write-Allocate
+    WriteThroughNoWriteAlloc {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
+    /// Normal Memory, Outer and Inner Cache are Write-Back, no Write-Allocate
+    WriteBackNoWriteAlloc {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
+    /// Normal Memory, Non-cacheable in Outer and Inner Caches
+    NonCacheable {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
     /// Implementation Defined
-    ImplementationDefined { shareable: bool },
+    ImplementationDefined {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
     /// Outer and Inner Write-Back, Write-Allocate
-    WriteBackWriteAllocate { shareable: bool },
-    /// Cacheable memory
+    WriteBackWriteAlloc {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
+    /// Normal Memory, where Inner and Outer cache have different settings
     Cacheable {
-        outer: CacheablePolicy,
-        inner: CacheablePolicy,
+        /// Settings for the Outer Cache
+        outer: CachePolicy,
+        /// Settings for the Inner Cache
+        inner: CachePolicy,
+        /// Is memory shareable (across multiple CPUs)
         shareable: bool,
     },
 }
@@ -276,13 +298,13 @@ impl MemAttr {
                 b: false,
                 s: false,
             },
-            MemAttr::WriteThroughNoWriteAllocate { shareable } => MemAttrBits {
+            MemAttr::WriteThroughNoWriteAlloc { shareable } => MemAttrBits {
                 tex: u3::from_u8(0b000),
                 c: true,
                 b: false,
                 s: *shareable,
             },
-            MemAttr::WriteBackNoWriteAllocate { shareable } => MemAttrBits {
+            MemAttr::WriteBackNoWriteAlloc { shareable } => MemAttrBits {
                 tex: u3::from_u8(0b000),
                 c: true,
                 b: true,
@@ -300,7 +322,7 @@ impl MemAttr {
                 b: false,
                 s: *shareable,
             },
-            MemAttr::WriteBackWriteAllocate { shareable } => MemAttrBits {
+            MemAttr::WriteBackWriteAlloc { shareable } => MemAttrBits {
                 tex: u3::from_u8(0b000),
                 c: true,
                 b: true,
@@ -338,20 +360,18 @@ impl MemAttrBits {
         match (self.tex.value(), self.c, self.b) {
             (0b000, false, false) => Some(MemAttr::StronglyOrdered),
             (0b000, false, true) => Some(MemAttr::Device { shareable: true }),
-            (0b000, true, false) => {
-                Some(MemAttr::WriteThroughNoWriteAllocate { shareable: self.s })
-            }
-            (0b000, true, true) => Some(MemAttr::WriteBackNoWriteAllocate { shareable: self.s }),
+            (0b000, true, false) => Some(MemAttr::WriteThroughNoWriteAlloc { shareable: self.s }),
+            (0b000, true, true) => Some(MemAttr::WriteBackNoWriteAlloc { shareable: self.s }),
             (0b001, false, false) => Some(MemAttr::NonCacheable { shareable: self.s }),
             (0b001, true, false) => Some(MemAttr::ImplementationDefined { shareable: self.s }),
-            (0b001, true, true) => Some(MemAttr::WriteBackWriteAllocate { shareable: self.s }),
+            (0b001, true, true) => Some(MemAttr::WriteBackWriteAlloc { shareable: self.s }),
             (0b010, false, false) => Some(MemAttr::Device { shareable: false }),
             (tex, c, b) if tex >= 0b100 => {
                 let outer = tex & 0b11;
                 let inner = ((c as u8) << 1) | (b as u8);
                 Some(MemAttr::Cacheable {
-                    outer: CacheablePolicy::new_with_raw_value(u2::from_u8(outer)),
-                    inner: CacheablePolicy::new_with_raw_value(u2::from_u8(inner)),
+                    outer: CachePolicy::new_with_raw_value(u2::from_u8(outer)),
+                    inner: CachePolicy::new_with_raw_value(u2::from_u8(inner)),
                     shareable: self.s,
                 })
             }
@@ -363,14 +383,20 @@ impl MemAttrBits {
     }
 }
 
-/// Describes the cache policy of a region
-#[derive(Debug, PartialEq, Eq)]
+/// Whether/how a region is cacheable
 #[bitbybit::bitenum(u2, exhaustive = true)]
-pub enum CacheablePolicy {
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+#[derive(Debug, PartialEq, Eq)]
+pub enum CachePolicy {
+    /// Non-cacheable
     NonCacheable = 0b00,
-    WriteBackWriteAllocate = 0b01,
-    WriteThroughNoWriteAllocate = 0b10,
-    WriteBackNoWriteAllocate = 0b11,
+    /// Write-Back Cacheable, Write-Allocate
+    WriteBackWriteAlloc = 0b01,
+    /// Write-Through Cacheable
+    WriteThroughNoWriteAlloc = 0b10,
+    /// Write-Back Cacheable, no Write-Allocate
+    WriteBackNoWriteAlloc = 0b11,
 }
 
 #[cfg(test)]
@@ -398,9 +424,9 @@ mod test {
     fn mem_attr_complex() {
         let mem_attr = MemAttr::Cacheable {
             // 0b01
-            outer: CacheablePolicy::WriteBackWriteAllocate,
+            outer: CachePolicy::WriteBackWriteAlloc,
             // 0b10
-            inner: CacheablePolicy::WriteThroughNoWriteAllocate,
+            inner: CachePolicy::WriteThroughNoWriteAlloc,
             shareable: true,
         };
         let mem_attr_bits = mem_attr.to_bits();
diff --git a/aarch32-cpu/src/pmsav8.rs b/aarch32-cpu/src/pmsav8.rs
index 91be34ed..5d03a24e 100644
--- a/aarch32-cpu/src/pmsav8.rs
+++ b/aarch32-cpu/src/pmsav8.rs
@@ -461,9 +461,9 @@ pub enum MemAttr {
     /// Normal memory
     NormalMemory {
         /// Controls outer access
-        outer: Cacheable,
+        outer: CachePolicy,
         /// Controls inner access
-        inner: Cacheable,
+        inner: CachePolicy,
     },
 }
 
@@ -484,23 +484,28 @@ impl MemAttr {
 
 /// Cacheability of a region
 #[derive(Debug, Clone, PartialEq, Eq)]
-pub enum Cacheable {
+pub enum CachePolicy {
+    /// Normal memory, Outer Write-Through Transient
     WriteThroughTransient(RwAllocPolicy),
+    /// Normal memory, Outer Write-Back Transient
     WriteBackTransient(RwAllocPolicy),
+    /// Normal memory, Outer Write-Through Non-transient
     WriteThroughNonTransient(RwAllocPolicy),
+    /// Normal memory, Outer Write-Back Non-transient
     WriteBackNonTransient(RwAllocPolicy),
+    /// Normal memory, Outer Non-cacheable
     NonCacheable,
 }
 
-impl Cacheable {
+impl CachePolicy {
     const fn to_bits(&self) -> u8 {
         #[allow(clippy::identity_op)]
         match self {
-            Cacheable::WriteThroughTransient(rw_alloc) => 0b0000 | (*rw_alloc as u8),
-            Cacheable::WriteBackTransient(rw_alloc) => 0b0100 | (*rw_alloc as u8),
-            Cacheable::WriteThroughNonTransient(rw_alloc) => 0b1000 | (*rw_alloc as u8),
-            Cacheable::WriteBackNonTransient(rw_alloc) => 0b1100 | (*rw_alloc as u8),
-            Cacheable::NonCacheable => 0b0100,
+            CachePolicy::WriteThroughTransient(rw_alloc) => 0b0000 | (*rw_alloc as u8),
+            CachePolicy::WriteBackTransient(rw_alloc) => 0b0100 | (*rw_alloc as u8),
+            CachePolicy::WriteThroughNonTransient(rw_alloc) => 0b1000 | (*rw_alloc as u8),
+            CachePolicy::WriteBackNonTransient(rw_alloc) => 0b1100 | (*rw_alloc as u8),
+            CachePolicy::NonCacheable => 0b0100,
         }
     }
 }
@@ -536,8 +541,8 @@ mod test {
     #[test]
     fn mem_attr_normal() {
         let mem_attr = MemAttr::NormalMemory {
-            outer: Cacheable::NonCacheable,
-            inner: Cacheable::WriteBackNonTransient(RwAllocPolicy::W),
+            outer: CachePolicy::NonCacheable,
+            inner: CachePolicy::WriteBackNonTransient(RwAllocPolicy::W),
         };
         assert_eq!(
             mem_attr.to_bits(),
diff --git a/aarch32-cpu/src/register/actlr.rs b/aarch32-cpu/src/register/actlr.rs
index d4b909f8..a8db1474 100644
--- a/aarch32-cpu/src/register/actlr.rs
+++ b/aarch32-cpu/src/register/actlr.rs
@@ -21,8 +21,8 @@ impl crate::register::SysRegRead for Actlr {}
 impl Actlr {
     #[inline]
     /// Reads ACTLR (*Auxiliary Control Register*)
-    pub fn read() -> Actlr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    pub fn read() -> Self {
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/actlr2.rs b/aarch32-cpu/src/register/actlr2.rs
index bc2b79f0..d71791df 100644
--- a/aarch32-cpu/src/register/actlr2.rs
+++ b/aarch32-cpu/src/register/actlr2.rs
@@ -21,8 +21,8 @@ impl crate::register::SysRegRead for Actlr2 {}
 impl Actlr2 {
     #[inline]
     /// Reads ACTLR2 (*Auxiliary Control Register 2*)
-    pub fn read() -> Actlr2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+    pub fn read() -> Self {
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/adfsr.rs b/aarch32-cpu/src/register/adfsr.rs
index 17406c93..383a03d0 100644
--- a/aarch32-cpu/src/register/adfsr.rs
+++ b/aarch32-cpu/src/register/adfsr.rs
@@ -22,7 +22,7 @@ impl Adfsr {
     #[inline]
     /// Reads ADFSR (*Auxiliary Data Fault Status Register*)
     pub fn read() -> Adfsr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/aidr.rs b/aarch32-cpu/src/register/aidr.rs
index d126d460..b46e4474 100644
--- a/aarch32-cpu/src/register/aidr.rs
+++ b/aarch32-cpu/src/register/aidr.rs
@@ -22,6 +22,6 @@ impl Aidr {
     #[inline]
     /// Reads AIDR (*Auxiliary ID Register*)
     pub fn read() -> Aidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/aifsr.rs b/aarch32-cpu/src/register/aifsr.rs
index dc99a22f..ceb1282e 100644
--- a/aarch32-cpu/src/register/aifsr.rs
+++ b/aarch32-cpu/src/register/aifsr.rs
@@ -22,7 +22,7 @@ impl Aifsr {
     #[inline]
     /// Reads AIFSR (*Auxiliary Instruction Fault Status Register*)
     pub fn read() -> Aifsr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/amair0.rs b/aarch32-cpu/src/register/amair0.rs
index 9f3ebfce..70c608f1 100644
--- a/aarch32-cpu/src/register/amair0.rs
+++ b/aarch32-cpu/src/register/amair0.rs
@@ -22,7 +22,7 @@ impl Amair0 {
     #[inline]
     /// Reads AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
     pub fn read() -> Amair0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/amair1.rs b/aarch32-cpu/src/register/amair1.rs
index 5a9e8d6b..ac098927 100644
--- a/aarch32-cpu/src/register/amair1.rs
+++ b/aarch32-cpu/src/register/amair1.rs
@@ -22,7 +22,7 @@ impl Amair1 {
     #[inline]
     /// Reads AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
     pub fn read() -> Amair1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hmpuir.rs b/aarch32-cpu/src/register/armv8r/hmpuir.rs
index 090fc4b6..3031363f 100644
--- a/aarch32-cpu/src/register/armv8r/hmpuir.rs
+++ b/aarch32-cpu/src/register/armv8r/hmpuir.rs
@@ -25,6 +25,6 @@ impl Hmpuir {
     #[inline]
     /// Reads HMPUIR (*Hyp MPU Type Register*)
     pub fn read() -> Hmpuir {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/armv8r/hprbar.rs b/aarch32-cpu/src/register/armv8r/hprbar.rs
index e313c1ef..cc2ed033 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar.rs
@@ -67,7 +67,7 @@ impl Hprbar {
     #[inline]
     /// Reads HPRBAR (*Hyp Protection Region Base Address Register*)
     pub fn read() -> Hprbar {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar0.rs b/aarch32-cpu/src/register/armv8r/hprbar0.rs
index 00161ab6..475347d2 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar0.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar0.rs
@@ -22,7 +22,7 @@ impl Hprbar0 {
     #[inline]
     /// Reads HPRBAR0 (*Hyp Protection Region Base Address Register 0*)
     pub fn read() -> Hprbar0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar1.rs b/aarch32-cpu/src/register/armv8r/hprbar1.rs
index f5c988a5..c3a2944e 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar1.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar1.rs
@@ -22,7 +22,7 @@ impl Hprbar1 {
     #[inline]
     /// Reads HPRBAR1 (*Hyp Protection Region Base Address Register 1*)
     pub fn read() -> Hprbar1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar10.rs b/aarch32-cpu/src/register/armv8r/hprbar10.rs
index 3167b274..82128351 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar10.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar10.rs
@@ -22,7 +22,7 @@ impl Hprbar10 {
     #[inline]
     /// Reads HPRBAR10 (*Hyp Protection Region Base Address Register 10*)
     pub fn read() -> Hprbar10 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar11.rs b/aarch32-cpu/src/register/armv8r/hprbar11.rs
index 8abca05c..2994341f 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar11.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar11.rs
@@ -22,7 +22,7 @@ impl Hprbar11 {
     #[inline]
     /// Reads HPRBAR11 (*Hyp Protection Region Base Address Register 11*)
     pub fn read() -> Hprbar11 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar12.rs b/aarch32-cpu/src/register/armv8r/hprbar12.rs
index 735a147c..342b8435 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar12.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar12.rs
@@ -22,7 +22,7 @@ impl Hprbar12 {
     #[inline]
     /// Reads HPRBAR12 (*Hyp Protection Region Base Address Register 12*)
     pub fn read() -> Hprbar12 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar13.rs b/aarch32-cpu/src/register/armv8r/hprbar13.rs
index 4afa8142..49a20d2c 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar13.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar13.rs
@@ -22,7 +22,7 @@ impl Hprbar13 {
     #[inline]
     /// Reads HPRBAR13 (*Hyp Protection Region Base Address Register 13*)
     pub fn read() -> Hprbar13 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar14.rs b/aarch32-cpu/src/register/armv8r/hprbar14.rs
index 9ae75ca2..2bbd7b41 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar14.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar14.rs
@@ -22,7 +22,7 @@ impl Hprbar14 {
     #[inline]
     /// Reads HPRBAR14 (*Hyp Protection Region Base Address Register 14*)
     pub fn read() -> Hprbar14 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar15.rs b/aarch32-cpu/src/register/armv8r/hprbar15.rs
index ce6e56d8..3d4aa1f7 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar15.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar15.rs
@@ -22,7 +22,7 @@ impl Hprbar15 {
     #[inline]
     /// Reads HPRBAR15 (*Hyp Protection Region Base Address Register 15*)
     pub fn read() -> Hprbar15 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar2.rs b/aarch32-cpu/src/register/armv8r/hprbar2.rs
index 1d4a1af7..220a258f 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar2.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar2.rs
@@ -22,7 +22,7 @@ impl Hprbar2 {
     #[inline]
     /// Reads HPRBAR2 (*Hyp Protection Region Base Address Register 2*)
     pub fn read() -> Hprbar2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar3.rs b/aarch32-cpu/src/register/armv8r/hprbar3.rs
index 208743d6..acae8c76 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar3.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar3.rs
@@ -22,7 +22,7 @@ impl Hprbar3 {
     #[inline]
     /// Reads HPRBAR3 (*Hyp Protection Region Base Address Register 3*)
     pub fn read() -> Hprbar3 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar4.rs b/aarch32-cpu/src/register/armv8r/hprbar4.rs
index 3476af55..0d9f2450 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar4.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar4.rs
@@ -22,7 +22,7 @@ impl Hprbar4 {
     #[inline]
     /// Reads HPRBAR4 (*Hyp Protection Region Base Address Register 4*)
     pub fn read() -> Hprbar4 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar5.rs b/aarch32-cpu/src/register/armv8r/hprbar5.rs
index ee606ac5..c491701d 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar5.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar5.rs
@@ -22,7 +22,7 @@ impl Hprbar5 {
     #[inline]
     /// Reads HPRBAR5 (*Hyp Protection Region Base Address Register 5*)
     pub fn read() -> Hprbar5 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar6.rs b/aarch32-cpu/src/register/armv8r/hprbar6.rs
index 743fdf59..9b54fe12 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar6.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar6.rs
@@ -22,7 +22,7 @@ impl Hprbar6 {
     #[inline]
     /// Reads HPRBAR6 (*Hyp Protection Region Base Address Register 6*)
     pub fn read() -> Hprbar6 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar7.rs b/aarch32-cpu/src/register/armv8r/hprbar7.rs
index 5ee4cce4..01436166 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar7.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar7.rs
@@ -22,7 +22,7 @@ impl Hprbar7 {
     #[inline]
     /// Reads HPRBAR7 (*Hyp Protection Region Base Address Register 7*)
     pub fn read() -> Hprbar7 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar8.rs b/aarch32-cpu/src/register/armv8r/hprbar8.rs
index a8404afc..4d9bfea8 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar8.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar8.rs
@@ -22,7 +22,7 @@ impl Hprbar8 {
     #[inline]
     /// Reads HPRBAR8 (*Hyp Protection Region Base Address Register 8*)
     pub fn read() -> Hprbar8 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprbar9.rs b/aarch32-cpu/src/register/armv8r/hprbar9.rs
index 93d07c80..1e168ab1 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar9.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar9.rs
@@ -22,7 +22,7 @@ impl Hprbar9 {
     #[inline]
     /// Reads HPRBAR9 (*Hyp Protection Region Base Address Register 9*)
     pub fn read() -> Hprbar9 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprenr.rs b/aarch32-cpu/src/register/armv8r/hprenr.rs
index ccc556b4..1328fc12 100644
--- a/aarch32-cpu/src/register/armv8r/hprenr.rs
+++ b/aarch32-cpu/src/register/armv8r/hprenr.rs
@@ -22,7 +22,7 @@ impl Hprenr {
     #[inline]
     /// Reads HPRENR (*Hyp MPU Region Enable Register*)
     pub fn read() -> Hprenr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar.rs b/aarch32-cpu/src/register/armv8r/hprlar.rs
index b4f4549c..6ed16724 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar.rs
@@ -32,7 +32,7 @@ impl Hprlar {
     #[inline]
     /// Reads HPRLAR (*Hyp Protection Region Limit Address Register*)
     pub fn read() -> Hprlar {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar0.rs b/aarch32-cpu/src/register/armv8r/hprlar0.rs
index cdfec7d6..f633b7ed 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar0.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar0.rs
@@ -22,7 +22,7 @@ impl Hprlar0 {
     #[inline]
     /// Reads HPRLAR0 (*Hyp Protection Region Limit Address Register 0*)
     pub fn read() -> Hprlar0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar1.rs b/aarch32-cpu/src/register/armv8r/hprlar1.rs
index 34dc23b7..226220ff 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar1.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar1.rs
@@ -22,7 +22,7 @@ impl Hprlar1 {
     #[inline]
     /// Reads HPRLAR1 (*Hyp Protection Region Limit Address Register 1*)
     pub fn read() -> Hprlar1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar10.rs b/aarch32-cpu/src/register/armv8r/hprlar10.rs
index e32f2055..9d593e37 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar10.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar10.rs
@@ -22,7 +22,7 @@ impl Hprlar10 {
     #[inline]
     /// Reads HPRLAR10 (*Hyp Protection Region Limit Address Register 10*)
     pub fn read() -> Hprlar10 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar11.rs b/aarch32-cpu/src/register/armv8r/hprlar11.rs
index 4685e3a8..1526adc3 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar11.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar11.rs
@@ -22,7 +22,7 @@ impl Hprlar11 {
     #[inline]
     /// Reads HPRLAR11 (*Hyp Protection Region Limit Address Register 11*)
     pub fn read() -> Hprlar11 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar12.rs b/aarch32-cpu/src/register/armv8r/hprlar12.rs
index 7b44a656..9ccbb7d9 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar12.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar12.rs
@@ -22,7 +22,7 @@ impl Hprlar12 {
     #[inline]
     /// Reads HPRLAR12 (*Hyp Protection Region Limit Address Register 12*)
     pub fn read() -> Hprlar12 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar13.rs b/aarch32-cpu/src/register/armv8r/hprlar13.rs
index ca44175a..10fc650a 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar13.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar13.rs
@@ -22,7 +22,7 @@ impl Hprlar13 {
     #[inline]
     /// Reads HPRLAR13 (*Hyp Protection Region Limit Address Register 13*)
     pub fn read() -> Hprlar13 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar14.rs b/aarch32-cpu/src/register/armv8r/hprlar14.rs
index 339d09d7..401643ab 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar14.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar14.rs
@@ -22,7 +22,7 @@ impl Hprlar14 {
     #[inline]
     /// Reads HPRLAR14 (*Hyp Protection Region Limit Address Register 14*)
     pub fn read() -> Hprlar14 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar15.rs b/aarch32-cpu/src/register/armv8r/hprlar15.rs
index e06fa459..543e8676 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar15.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar15.rs
@@ -22,7 +22,7 @@ impl Hprlar15 {
     #[inline]
     /// Reads HPRLAR15 (*Hyp Protection Region Limit Address Register 15*)
     pub fn read() -> Hprlar15 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar2.rs b/aarch32-cpu/src/register/armv8r/hprlar2.rs
index ecc55c13..b682e4da 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar2.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar2.rs
@@ -22,7 +22,7 @@ impl Hprlar2 {
     #[inline]
     /// Reads HPRLAR2 (*Hyp Protection Region Limit Address Register 2*)
     pub fn read() -> Hprlar2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar3.rs b/aarch32-cpu/src/register/armv8r/hprlar3.rs
index 2d80fb5d..2b194908 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar3.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar3.rs
@@ -22,7 +22,7 @@ impl Hprlar3 {
     #[inline]
     /// Reads HPRLAR3 (*Hyp Protection Region Limit Address Register 3*)
     pub fn read() -> Hprlar3 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar4.rs b/aarch32-cpu/src/register/armv8r/hprlar4.rs
index 840ea92e..5eaaa775 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar4.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar4.rs
@@ -22,7 +22,7 @@ impl Hprlar4 {
     #[inline]
     /// Reads HPRLAR4 (*Hyp Protection Region Limit Address Register 4*)
     pub fn read() -> Hprlar4 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar5.rs b/aarch32-cpu/src/register/armv8r/hprlar5.rs
index 254d358f..24fb6ea0 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar5.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar5.rs
@@ -22,7 +22,7 @@ impl Hprlar5 {
     #[inline]
     /// Reads HPRLAR5 (*Hyp Protection Region Limit Address Register 5*)
     pub fn read() -> Hprlar5 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar6.rs b/aarch32-cpu/src/register/armv8r/hprlar6.rs
index 3f35515f..b562f9ae 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar6.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar6.rs
@@ -22,7 +22,7 @@ impl Hprlar6 {
     #[inline]
     /// Reads HPRLAR6 (*Hyp Protection Region Limit Address Register 6*)
     pub fn read() -> Hprlar6 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar7.rs b/aarch32-cpu/src/register/armv8r/hprlar7.rs
index bd57de79..9633c638 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar7.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar7.rs
@@ -22,7 +22,7 @@ impl Hprlar7 {
     #[inline]
     /// Reads HPRLAR7 (*Hyp Protection Region Limit Address Register 7*)
     pub fn read() -> Hprlar7 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar8.rs b/aarch32-cpu/src/register/armv8r/hprlar8.rs
index 67f5246a..8f38614f 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar8.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar8.rs
@@ -22,7 +22,7 @@ impl Hprlar8 {
     #[inline]
     /// Reads HPRLAR8 (*Hyp Protection Region Limit Address Register 8*)
     pub fn read() -> Hprlar8 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprlar9.rs b/aarch32-cpu/src/register/armv8r/hprlar9.rs
index 00459760..3bd79580 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar9.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar9.rs
@@ -22,7 +22,7 @@ impl Hprlar9 {
     #[inline]
     /// Reads HPRLAR9 (*Hyp Protection Region Limit Address Register 9*)
     pub fn read() -> Hprlar9 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/hprselr.rs b/aarch32-cpu/src/register/armv8r/hprselr.rs
index ea2c18be..34c49f89 100644
--- a/aarch32-cpu/src/register/armv8r/hprselr.rs
+++ b/aarch32-cpu/src/register/armv8r/hprselr.rs
@@ -22,7 +22,7 @@ impl Hprselr {
     #[inline]
     /// Reads HPRSELR (*Hyp Protection Region Selection Register*)
     pub fn read() -> Hprselr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar.rs b/aarch32-cpu/src/register/armv8r/prbar.rs
index 4acabd14..40b6c3b0 100644
--- a/aarch32-cpu/src/register/armv8r/prbar.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar.rs
@@ -67,7 +67,7 @@ impl Prbar {
     #[inline]
     /// Reads PRBAR (*Protection Region Base Address Register*)
     pub fn read() -> Prbar {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar0.rs b/aarch32-cpu/src/register/armv8r/prbar0.rs
index ed78bf45..3a8f8a50 100644
--- a/aarch32-cpu/src/register/armv8r/prbar0.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar0.rs
@@ -22,7 +22,7 @@ impl Prbar0 {
     #[inline]
     /// Reads PRBAR0 (*Protection Region Base Address Register 0*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar1.rs b/aarch32-cpu/src/register/armv8r/prbar1.rs
index 2b343fc5..4c23fa13 100644
--- a/aarch32-cpu/src/register/armv8r/prbar1.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar1.rs
@@ -22,7 +22,7 @@ impl Prbar1 {
     #[inline]
     /// Reads PRBAR1 (*Protection Region Base Address Register 1*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar10.rs b/aarch32-cpu/src/register/armv8r/prbar10.rs
index 7f606a68..499d57fe 100644
--- a/aarch32-cpu/src/register/armv8r/prbar10.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar10.rs
@@ -22,7 +22,7 @@ impl Prbar10 {
     #[inline]
     /// Reads PRBAR10 (*Protection Region Base Address Register 10*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar11.rs b/aarch32-cpu/src/register/armv8r/prbar11.rs
index e919e7dc..b2508467 100644
--- a/aarch32-cpu/src/register/armv8r/prbar11.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar11.rs
@@ -22,7 +22,7 @@ impl Prbar11 {
     #[inline]
     /// Reads PRBAR11 (*Protection Region Base Address Register 11*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar12.rs b/aarch32-cpu/src/register/armv8r/prbar12.rs
index c681d98f..4f987ca6 100644
--- a/aarch32-cpu/src/register/armv8r/prbar12.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar12.rs
@@ -22,7 +22,7 @@ impl Prbar12 {
     #[inline]
     /// Reads PRBAR12 (*Protection Region Base Address Register 12*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar13.rs b/aarch32-cpu/src/register/armv8r/prbar13.rs
index 586b0b1c..0590786a 100644
--- a/aarch32-cpu/src/register/armv8r/prbar13.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar13.rs
@@ -22,7 +22,7 @@ impl Prbar13 {
     #[inline]
     /// Reads PRBAR13 (*Protection Region Base Address Register 13*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar14.rs b/aarch32-cpu/src/register/armv8r/prbar14.rs
index 23a82437..97924fe9 100644
--- a/aarch32-cpu/src/register/armv8r/prbar14.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar14.rs
@@ -22,7 +22,7 @@ impl Prbar14 {
     #[inline]
     /// Reads PRBAR14 (*Protection Region Base Address Register 14*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar15.rs b/aarch32-cpu/src/register/armv8r/prbar15.rs
index 59b67daf..6cf39eee 100644
--- a/aarch32-cpu/src/register/armv8r/prbar15.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar15.rs
@@ -22,7 +22,7 @@ impl Prbar15 {
     #[inline]
     /// Reads PRBAR15 (*Protection Region Base Address Register 15*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar2.rs b/aarch32-cpu/src/register/armv8r/prbar2.rs
index bf4139af..c31d099d 100644
--- a/aarch32-cpu/src/register/armv8r/prbar2.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar2.rs
@@ -22,7 +22,7 @@ impl Prbar2 {
     #[inline]
     /// Reads PRBAR0 (*Protection Region Base Address Register 2*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar3.rs b/aarch32-cpu/src/register/armv8r/prbar3.rs
index faa2c27c..b8bc9a98 100644
--- a/aarch32-cpu/src/register/armv8r/prbar3.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar3.rs
@@ -22,7 +22,7 @@ impl Prbar3 {
     #[inline]
     /// Reads PRBAR3 (*Protection Region Base Address Register 3*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar4.rs b/aarch32-cpu/src/register/armv8r/prbar4.rs
index d854d8f0..99bcc737 100644
--- a/aarch32-cpu/src/register/armv8r/prbar4.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar4.rs
@@ -22,7 +22,7 @@ impl Prbar4 {
     #[inline]
     /// Reads PRBAR4 (*Protection Region Base Address Register 4*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar5.rs b/aarch32-cpu/src/register/armv8r/prbar5.rs
index ea498520..c0dbde7d 100644
--- a/aarch32-cpu/src/register/armv8r/prbar5.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar5.rs
@@ -22,7 +22,7 @@ impl Prbar5 {
     #[inline]
     /// Reads PRBAR5 (*Protection Region Base Address Register 5*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar6.rs b/aarch32-cpu/src/register/armv8r/prbar6.rs
index 52ceb526..6f1d6f42 100644
--- a/aarch32-cpu/src/register/armv8r/prbar6.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar6.rs
@@ -22,7 +22,7 @@ impl Prbar6 {
     #[inline]
     /// Reads PRBAR6 (*Protection Region Base Address Register 6*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar7.rs b/aarch32-cpu/src/register/armv8r/prbar7.rs
index 27db0d5a..611746d9 100644
--- a/aarch32-cpu/src/register/armv8r/prbar7.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar7.rs
@@ -22,7 +22,7 @@ impl Prbar7 {
     #[inline]
     /// Reads PRBAR7 (*Protection Region Base Address Register 7*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar8.rs b/aarch32-cpu/src/register/armv8r/prbar8.rs
index 46bd9659..0437a639 100644
--- a/aarch32-cpu/src/register/armv8r/prbar8.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar8.rs
@@ -22,7 +22,7 @@ impl Prbar8 {
     #[inline]
     /// Reads PRBAR8 (*Protection Region Base Address Register 8*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prbar9.rs b/aarch32-cpu/src/register/armv8r/prbar9.rs
index eabe9861..5d023a94 100644
--- a/aarch32-cpu/src/register/armv8r/prbar9.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar9.rs
@@ -22,7 +22,7 @@ impl Prbar9 {
     #[inline]
     /// Reads PRBAR9 (*Protection Region Base Address Register 9*)
     pub fn read() -> Prbar {
-        unsafe { Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prbar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar.rs b/aarch32-cpu/src/register/armv8r/prlar.rs
index 6285fefd..b8526e2b 100644
--- a/aarch32-cpu/src/register/armv8r/prlar.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar.rs
@@ -32,7 +32,7 @@ impl Prlar {
     #[inline]
     /// Reads PRLAR (*Protection Region Limit Address Register*)
     pub fn read() -> Prlar {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar0.rs b/aarch32-cpu/src/register/armv8r/prlar0.rs
index 48c3a4e6..c0f5df4a 100644
--- a/aarch32-cpu/src/register/armv8r/prlar0.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar0.rs
@@ -22,7 +22,7 @@ impl Prlar0 {
     #[inline]
     /// Reads PRLAR0 (*Protection Region Limit Address Register 0*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar1.rs b/aarch32-cpu/src/register/armv8r/prlar1.rs
index 09ef217b..499c6295 100644
--- a/aarch32-cpu/src/register/armv8r/prlar1.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar1.rs
@@ -22,7 +22,7 @@ impl Prlar1 {
     #[inline]
     /// Reads PRLAR1 (*Protection Region Limit Address Register 1*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar10.rs b/aarch32-cpu/src/register/armv8r/prlar10.rs
index ea3e10ca..f2068955 100644
--- a/aarch32-cpu/src/register/armv8r/prlar10.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar10.rs
@@ -22,7 +22,7 @@ impl Prlar10 {
     #[inline]
     /// Reads PRLAR10 (*Protection Region Limit Address Register 10*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar11.rs b/aarch32-cpu/src/register/armv8r/prlar11.rs
index 0be023a0..c80bf89a 100644
--- a/aarch32-cpu/src/register/armv8r/prlar11.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar11.rs
@@ -22,7 +22,7 @@ impl Prlar11 {
     #[inline]
     /// Reads PRLAR11 (*Protection Region Limit Address Register 11*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar12.rs b/aarch32-cpu/src/register/armv8r/prlar12.rs
index 69150ce4..4236d4b6 100644
--- a/aarch32-cpu/src/register/armv8r/prlar12.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar12.rs
@@ -22,7 +22,7 @@ impl Prlar12 {
     #[inline]
     /// Reads PRLAR12 (*Protection Region Limit Address Register 12*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar13.rs b/aarch32-cpu/src/register/armv8r/prlar13.rs
index 19e96389..1ce18ebd 100644
--- a/aarch32-cpu/src/register/armv8r/prlar13.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar13.rs
@@ -22,7 +22,7 @@ impl Prlar13 {
     #[inline]
     /// Reads PRLAR13 (*Protection Region Limit Address Register 13*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar14.rs b/aarch32-cpu/src/register/armv8r/prlar14.rs
index a75497df..04831c8a 100644
--- a/aarch32-cpu/src/register/armv8r/prlar14.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar14.rs
@@ -22,7 +22,7 @@ impl Prlar14 {
     #[inline]
     /// Reads PRLAR14 (*Protection Region Limit Address Register 14*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar15.rs b/aarch32-cpu/src/register/armv8r/prlar15.rs
index f0b2267c..5cb75734 100644
--- a/aarch32-cpu/src/register/armv8r/prlar15.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar15.rs
@@ -22,7 +22,7 @@ impl Prlar15 {
     #[inline]
     /// Reads PRLAR15 (*Protection Region Limit Address Register 15*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar2.rs b/aarch32-cpu/src/register/armv8r/prlar2.rs
index 625199b2..12fcd3db 100644
--- a/aarch32-cpu/src/register/armv8r/prlar2.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar2.rs
@@ -22,7 +22,7 @@ impl Prlar2 {
     #[inline]
     /// Reads PRLAR2 (*Protection Region Limit Address Register 2*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar3.rs b/aarch32-cpu/src/register/armv8r/prlar3.rs
index 2276b859..9aa51515 100644
--- a/aarch32-cpu/src/register/armv8r/prlar3.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar3.rs
@@ -22,7 +22,7 @@ impl Prlar3 {
     #[inline]
     /// Reads PRLAR3 (*Protection Region Limit Address Register 3*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar4.rs b/aarch32-cpu/src/register/armv8r/prlar4.rs
index 86d5fd52..23ff3799 100644
--- a/aarch32-cpu/src/register/armv8r/prlar4.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar4.rs
@@ -22,7 +22,7 @@ impl Prlar4 {
     #[inline]
     /// Reads PRLAR4 (*Protection Region Limit Address Register 4*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar5.rs b/aarch32-cpu/src/register/armv8r/prlar5.rs
index 65f55ae4..f6263464 100644
--- a/aarch32-cpu/src/register/armv8r/prlar5.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar5.rs
@@ -22,7 +22,7 @@ impl Prlar5 {
     #[inline]
     /// Reads PRLAR5 (*Protection Region Limit Address Register 5*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar6.rs b/aarch32-cpu/src/register/armv8r/prlar6.rs
index 2882ba6f..e4bece75 100644
--- a/aarch32-cpu/src/register/armv8r/prlar6.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar6.rs
@@ -22,7 +22,7 @@ impl Prlar6 {
     #[inline]
     /// Reads PRLAR6 (*Protection Region Limit Address Register 6*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar7.rs b/aarch32-cpu/src/register/armv8r/prlar7.rs
index f0c82252..a99209d3 100644
--- a/aarch32-cpu/src/register/armv8r/prlar7.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar7.rs
@@ -22,7 +22,7 @@ impl Prlar7 {
     #[inline]
     /// Reads PRLAR7 (*Protection Region Limit Address Register 7*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar8.rs b/aarch32-cpu/src/register/armv8r/prlar8.rs
index d488cf3d..6c2f8fda 100644
--- a/aarch32-cpu/src/register/armv8r/prlar8.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar8.rs
@@ -22,7 +22,7 @@ impl Prlar8 {
     #[inline]
     /// Reads PRLAR8 (*Protection Region Limit Address Register 8*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prlar9.rs b/aarch32-cpu/src/register/armv8r/prlar9.rs
index ad1e0eb7..ece1f7eb 100644
--- a/aarch32-cpu/src/register/armv8r/prlar9.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar9.rs
@@ -22,7 +22,7 @@ impl Prlar9 {
     #[inline]
     /// Reads PRLAR9 (*Protection Region Limit Address Register 9*)
     pub fn read() -> Prlar {
-        unsafe { Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Prlar::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/prselr.rs b/aarch32-cpu/src/register/armv8r/prselr.rs
index 01f3e6c0..aa329a0b 100644
--- a/aarch32-cpu/src/register/armv8r/prselr.rs
+++ b/aarch32-cpu/src/register/armv8r/prselr.rs
@@ -22,7 +22,7 @@ impl Prselr {
     #[inline]
     /// Reads PRSELR (*Protection Region Selection Register*)
     pub fn read() -> Prselr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/armv8r/vbar.rs b/aarch32-cpu/src/register/armv8r/vbar.rs
index a3998f9e..1fb39f40 100644
--- a/aarch32-cpu/src/register/armv8r/vbar.rs
+++ b/aarch32-cpu/src/register/armv8r/vbar.rs
@@ -27,8 +27,7 @@ impl Vbar {
     /// Read VBAR (*Vector Base Address Register*)
     #[inline]
     pub fn read() -> Vbar {
-        // Safety: Reading this register has no side-effects and is atomic
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 
     /// Write VBAR (*Vector Base Address Register*)
diff --git a/aarch32-cpu/src/register/bpiall.rs b/aarch32-cpu/src/register/bpiall.rs
index 7f0ce864..71d68659 100644
--- a/aarch32-cpu/src/register/bpiall.rs
+++ b/aarch32-cpu/src/register/bpiall.rs
@@ -17,6 +17,7 @@ impl crate::register::SysRegWrite for BpIAll {}
 
 impl BpIAll {
     #[inline]
+    /// Writes 0 to BPIALL (*Branch Predictor Invalidate All*) to trigger operation
     pub fn write() {
         unsafe { <Self as crate::register::SysRegWrite>::write_raw(0) }
     }
diff --git a/aarch32-cpu/src/register/ccsidr.rs b/aarch32-cpu/src/register/ccsidr.rs
index f9955761..49e8eb48 100644
--- a/aarch32-cpu/src/register/ccsidr.rs
+++ b/aarch32-cpu/src/register/ccsidr.rs
@@ -7,18 +7,25 @@ use arbitrary_int::{u10, u15, u3};
 #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Ccsidr {
+    /// Indicates whether the cache level supports Write-Through
     #[bit(31, rw)]
     write_through: bool,
+    /// Indicates whether the cache level supports Write-Back
     #[bit(30, rw)]
     write_back: bool,
+    /// Indicates whether the cache level supports Read-Allocation
     #[bit(29, rw)]
     read_alloc: bool,
+    /// Indicates whether the cache level supports Write-Allocation
     #[bit(28, rw)]
     write_alloc: bool,
+    /// Number of sets in cache, minus 1
     #[bits(13..=27, rw)]
     num_sets: u15,
+    /// Associativity of cache, minus 1
     #[bits(3..=12, rw)]
     associativity: u10,
+    /// log2(cache line size in words), minus 1
     #[bits(0..=2, rw)]
     line_size: u3,
 }
@@ -37,6 +44,6 @@ impl Ccsidr {
     #[inline]
     /// Reads CCSIDR (*Current Cache Size ID Register*)
     pub fn read() -> Ccsidr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/clidr.rs b/aarch32-cpu/src/register/clidr.rs
index 25b78031..5b728405 100644
--- a/aarch32-cpu/src/register/clidr.rs
+++ b/aarch32-cpu/src/register/clidr.rs
@@ -22,6 +22,6 @@ impl Clidr {
     #[inline]
     /// Reads CLIDR (*Cache Level ID Register*)
     pub fn read() -> Clidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/contextidr.rs b/aarch32-cpu/src/register/contextidr.rs
index 9c503fec..e038d7d7 100644
--- a/aarch32-cpu/src/register/contextidr.rs
+++ b/aarch32-cpu/src/register/contextidr.rs
@@ -22,7 +22,7 @@ impl Contextidr {
     #[inline]
     /// Reads CONTEXTIDR (*Context ID Register*)
     pub fn read() -> Contextidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/cpacr.rs b/aarch32-cpu/src/register/cpacr.rs
index 29a5c553..8aad1fb2 100644
--- a/aarch32-cpu/src/register/cpacr.rs
+++ b/aarch32-cpu/src/register/cpacr.rs
@@ -22,7 +22,7 @@ impl Cpacr {
     #[inline]
     /// Reads CPACR (*Architectural Feature Access Control Register*)
     pub fn read() -> Cpacr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/cpsr.rs b/aarch32-cpu/src/register/cpsr.rs
index 718f0e35..ead73586 100644
--- a/aarch32-cpu/src/register/cpsr.rs
+++ b/aarch32-cpu/src/register/cpsr.rs
@@ -84,7 +84,7 @@ impl Cpsr {
     )]
     pub fn read() -> Self {
         let r: u32;
-        // Safety: Reading this register has no side-effects and is atomic
+
         #[cfg(target_arch = "arm")]
         unsafe {
             core::arch::asm!("mrs {}, CPSR", out(reg) r, options(nomem, nostack, preserves_flags));
diff --git a/aarch32-cpu/src/register/csselr.rs b/aarch32-cpu/src/register/csselr.rs
index eed48318..6a72f0e2 100644
--- a/aarch32-cpu/src/register/csselr.rs
+++ b/aarch32-cpu/src/register/csselr.rs
@@ -7,8 +7,11 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// Type of processor cache
 pub enum CacheType {
+    /// Data or Unified Cache
     DataOrUnified = 0,
+    /// Instruction Cache
     Instruction = 1,
 }
 
@@ -20,6 +23,7 @@ pub struct Csselr {
     /// 0 for L1 cache, 1 for L2, etc.
     #[bits(1..=3, rw)]
     level: u3,
+    /// The type of cache
     #[bit(0, rw)]
     cache_type: CacheType,
 }
@@ -38,7 +42,7 @@ impl Csselr {
     #[inline]
     /// Reads CSSELR (*Cache Size Selection Register*)
     pub fn read() -> Csselr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/ctr.rs b/aarch32-cpu/src/register/ctr.rs
index 14b9c1bf..ba9d9c34 100644
--- a/aarch32-cpu/src/register/ctr.rs
+++ b/aarch32-cpu/src/register/ctr.rs
@@ -22,6 +22,6 @@ impl Ctr {
     #[inline]
     /// Reads CTR (*Cache Type Register*)
     pub fn read() -> Ctr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/dacr.rs b/aarch32-cpu/src/register/dacr.rs
index 1c52743e..ec33466c 100644
--- a/aarch32-cpu/src/register/dacr.rs
+++ b/aarch32-cpu/src/register/dacr.rs
@@ -6,6 +6,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Dacr {
+    /// An array of bits controlling access to each of the 16 domains
     #[bits(0..=1, rw)]
     d: [DomainAccess; 16],
 }
@@ -40,7 +41,7 @@ impl Dacr {
     #[inline]
     /// Reads DACR (*Domain Access Control Register*)
     pub fn read() -> Dacr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/dccimvac.rs b/aarch32-cpu/src/register/dccimvac.rs
index 9cd5f18e..6df24fca 100644
--- a/aarch32-cpu/src/register/dccimvac.rs
+++ b/aarch32-cpu/src/register/dccimvac.rs
@@ -1,7 +1,8 @@
-//! Code for managing DCCIMVAC (*Clean And Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+//! Code for managing DCCIMVAC (*Data Cache line Clean and Invalidate by VA to PoC Register*)
 
 use crate::register::{SysReg, SysRegWrite};
 
+/// DCCIMVAC (*Data Cache line Clean and Invalidate by VA to PoC Register*)
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -9,6 +10,7 @@ pub struct Dccimvac(pub u32);
 
 impl Dccimvac {
     #[inline]
+    /// Create a new DCCIMVAC containing the address to clean and invalidate
     pub const fn new(addr: u32) -> Self {
         Self(addr)
     }
@@ -26,7 +28,7 @@ impl crate::register::SysRegWrite for Dccimvac {}
 
 impl Dccimvac {
     #[inline]
-    /// Writes DCCIMVAC (*Clean And Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+    /// Writes DCCIMVAC (*Data Cache line Clean and Invalidate by VA to PoC Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dccisw.rs b/aarch32-cpu/src/register/dccisw.rs
index e8152f24..987686a6 100644
--- a/aarch32-cpu/src/register/dccisw.rs
+++ b/aarch32-cpu/src/register/dccisw.rs
@@ -1,4 +1,4 @@
-//! Code for managing DCCISW (*Clean and Invalidate Data or Unified cache line by Set/Way.*)
+//! Code for managing DCCISW (*Data Cache line Clean and Invalidate by Set/Way Register*)
 
 use arbitrary_int::u3;
 
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCCISW (*Data Cache line Clean and Invalidate by Set/Way Register*)
 pub struct Dccisw(pub u32);
 
 impl Dccisw {
@@ -52,7 +53,7 @@ impl crate::register::SysRegWrite for Dccisw {}
 
 impl Dccisw {
     #[inline]
-    /// Writes DCCISW (*Clean and Invalidate data or unified cache line by set/way.*)
+    /// Writes DCCISW (*Data Cache line Clean and Invalidate by Set/Way Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dccmvac.rs b/aarch32-cpu/src/register/dccmvac.rs
index abf7ad27..b24bb507 100644
--- a/aarch32-cpu/src/register/dccmvac.rs
+++ b/aarch32-cpu/src/register/dccmvac.rs
@@ -1,14 +1,16 @@
-//! Code for managing DCCMVAC (*Clean Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+//! Code for managing DCCMVAC (*Data Cache line Clean by VA to PoC Register*)
 
 use crate::register::{SysReg, SysRegWrite};
 
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCCMVAC (*Data Cache line Clean by VA to PoC Register*)
 pub struct Dccmvac(pub u32);
 
 impl Dccmvac {
     #[inline]
+    /// Create a new DCCMVAC containing the Virtual Address to clean
     pub const fn new(addr: u32) -> Self {
         Self(addr)
     }
@@ -26,7 +28,7 @@ impl crate::register::SysRegWrite for Dccmvac {}
 
 impl Dccmvac {
     #[inline]
-    /// Writes DCCMVAC (*Clean Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+    /// Writes DCCMVAC (*Data Cache line Clean by VA to PoC Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dccmvau.rs b/aarch32-cpu/src/register/dccmvau.rs
index 98fdc70e..8c1f3ecb 100644
--- a/aarch32-cpu/src/register/dccmvau.rs
+++ b/aarch32-cpu/src/register/dccmvau.rs
@@ -1,14 +1,16 @@
-//! Code for managing DCCMVAU (*Clean Data Cache Or Unified Cache Line by MVA to Point of Unification.*)
+//! Code for managing DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
 
 use crate::register::{SysReg, SysRegWrite};
 
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
 pub struct Dccmvau(pub u32);
 
 impl Dccmvau {
     #[inline]
+    /// Create a new DCCMVAU value containing the Virtual Address to clean
     pub const fn new(addr: u32) -> Self {
         Self(addr)
     }
@@ -26,7 +28,7 @@ impl crate::register::SysRegWrite for Dccmvau {}
 
 impl Dccmvau {
     #[inline]
-    /// Writes DCCMVAU (*Clean Data Cache Or Unified Cache Line by MVA to Point of Unification.*)
+    /// Writes DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dccsw.rs b/aarch32-cpu/src/register/dccsw.rs
index 77f58b9e..40817a1e 100644
--- a/aarch32-cpu/src/register/dccsw.rs
+++ b/aarch32-cpu/src/register/dccsw.rs
@@ -1,4 +1,4 @@
-//! Code for managing DCCSW (*Clean Data or Unified Cache line by Set/Way.*)
+//! Code for managing DCCSW (*Data Cache line Clean by Set/Way Register*)
 
 use arbitrary_int::u3;
 
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCCSW (*Data Cache line Clean by Set/Way Register*)
 pub struct Dccsw(pub u32);
 
 impl Dccsw {
@@ -52,7 +53,7 @@ impl crate::register::SysRegWrite for Dccsw {}
 
 impl Dccsw {
     #[inline]
-    /// Writes DCCSW (*Clean Data or Unified Cache line by Set/Way.*)
+    /// Writes DCCSW (*Data Cache line Clean by Set/Way Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dcimvac.rs b/aarch32-cpu/src/register/dcimvac.rs
index 9848585a..a86f4080 100644
--- a/aarch32-cpu/src/register/dcimvac.rs
+++ b/aarch32-cpu/src/register/dcimvac.rs
@@ -1,14 +1,16 @@
-//! Code for managing DCIMVAC (*Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+//! Code for managing DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
 
 use crate::register::{SysReg, SysRegWrite};
 
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
 pub struct Dcimvac(pub u32);
 
 impl Dcimvac {
     #[inline]
+    /// Create a new DCIMVAC value, given an address
     pub const fn new(addr: u32) -> Self {
         Self(addr)
     }
@@ -26,7 +28,7 @@ impl crate::register::SysRegWrite for Dcimvac {}
 
 impl Dcimvac {
     #[inline]
-    /// Writes DCIMVAC (*Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+    /// Writes DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dcisw.rs b/aarch32-cpu/src/register/dcisw.rs
index 444b79d4..1cfbd2f6 100644
--- a/aarch32-cpu/src/register/dcisw.rs
+++ b/aarch32-cpu/src/register/dcisw.rs
@@ -1,4 +1,4 @@
-//! Code for managing DCISW (*Invalidate Data or Unified Cache line by Set/Way.*)
+//! Code for managing DCISW (*Data Cache line Invalidate by Set/Way Register*)
 
 use arbitrary_int::u3;
 
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCISW (*Data Cache line Invalidate by Set/Way Register*)
 pub struct Dcisw(pub u32);
 
 impl Dcisw {
@@ -52,7 +53,7 @@ impl crate::register::SysRegWrite for Dcisw {}
 
 impl Dcisw {
     #[inline]
-    /// Writes DCSW (*Invalidate Data or Unified Cache line by Set/Way.*)
+    /// Writes DCSW (*Data Cache line Invalidate by Set/Way Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dfar.rs b/aarch32-cpu/src/register/dfar.rs
index 7fa38db9..b9bb544d 100644
--- a/aarch32-cpu/src/register/dfar.rs
+++ b/aarch32-cpu/src/register/dfar.rs
@@ -22,7 +22,7 @@ impl Dfar {
     #[inline]
     /// Reads DFAR (*Data Fault Address Register*)
     pub fn read() -> Dfar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/dfsr.rs b/aarch32-cpu/src/register/dfsr.rs
index fe132db2..dfed2030 100644
--- a/aarch32-cpu/src/register/dfsr.rs
+++ b/aarch32-cpu/src/register/dfsr.rs
@@ -92,18 +92,31 @@ pub struct Dfsr {
 #[derive(Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum DfsrStatus {
+    /// Alignment fault
     AlignmentFault = 1,
+    /// Debug Exception
     Debug = 2,
+    /// Alternate value for Alignment fault
     AlignmentAlt = 3,
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 5,
+    /// Translation fault, level 2
     TranslationFaultSecondLevel = 7,
+    /// Synchronous External Abort
     SyncExtAbort = 8,
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 9,
+    /// Alternate value for Synchronous External Abort
     SyncExtAbortAlt = 10,
+    /// Domain fault, level 2
     DomainFaultSecondLevel = 11,
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 13,
+    /// Synchronous External abort, on translation table walk, level 2
     SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
+    /// Permission fault, level 2
     PermissionFaultSecondLevel = 15,
 }
 
@@ -185,11 +198,11 @@ pub enum DfsrStatus {
     AlignmentFault = 0b00001,
     /// Debug exception.
     Debug = 0b00010,
-    /// Access flag fault, level 1.
+    /// Access flag fault, level 1
     AccessFlagFaultFirstLevel = 0b00011,
     /// Fault on instruction cache maintenance.
     CacheMaintenance = 0b00100,
-    /// Translation fault, level 1.
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 0b00101,
     /// Access flag fault, level 2.
     AccessFlagFaultSecondLevel = 0b00110,
@@ -197,13 +210,13 @@ pub enum DfsrStatus {
     TranslationFaultSecondLevel = 0b00111,
     /// Synchronous External abort, not on translation table walk.
     SyncExtAbort = 0b01000,
-    /// Domain fault, level 1.
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 0b01001,
     /// Domain fault, level 2.
     DomainFaultSecondLevel = 0b01011,
-    /// Synchronous External abort, on translation table walk, level 1.
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 0b01100,
-    /// Permission fault, level 1.
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 0b01101,
     /// Synchronous External abort, on translation table walk, level 2.
     SyncExtAbortOnTranslationTableWalkSecondLevel = 0b01110,
@@ -217,7 +230,7 @@ pub enum DfsrStatus {
     SErrorParityEccError = 0b11000,
     /// Synchronous parity or ECC error on memory access, not on translation table walk.
     SyncParErrorOnMemAccess = 0b11001,
-    /// Synchronous parity or ECC error on translation table walk, level 1.
+    /// Synchronous parity or ECC error on translation table walk, level 1
     SyncParErrorOnTranslationTableWalkFirstLevel = 0b11100,
     /// Synchronous parity or ECC error on translation table walk, level 2.
     SyncParErrorOnTranslationTableWalkSecondLevel = 0b11110,
@@ -263,7 +276,7 @@ impl Dfsr {
     #[inline]
     /// Reads DFSR (*Data Fault Status Register*)
     pub fn read() -> Dfsr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/dlr.rs b/aarch32-cpu/src/register/dlr.rs
index 03c7f535..a6ae6eff 100644
--- a/aarch32-cpu/src/register/dlr.rs
+++ b/aarch32-cpu/src/register/dlr.rs
@@ -22,7 +22,7 @@ impl Dlr {
     #[inline]
     /// Reads DLR (*Debug Link Register*)
     pub fn read() -> Dlr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/dracr.rs b/aarch32-cpu/src/register/dracr.rs
index 5edd99cc..f11e28a1 100644
--- a/aarch32-cpu/src/register/dracr.rs
+++ b/aarch32-cpu/src/register/dracr.rs
@@ -44,7 +44,7 @@ impl Dracr {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Dracr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/drbar.rs b/aarch32-cpu/src/register/drbar.rs
index 5e5f85f6..0edf080e 100644
--- a/aarch32-cpu/src/register/drbar.rs
+++ b/aarch32-cpu/src/register/drbar.rs
@@ -25,7 +25,7 @@ impl Drbar {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Drbar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/drsr.rs b/aarch32-cpu/src/register/drsr.rs
index b0d893c8..c9f2761e 100644
--- a/aarch32-cpu/src/register/drsr.rs
+++ b/aarch32-cpu/src/register/drsr.rs
@@ -77,6 +77,9 @@ pub enum RegionSize {
 }
 
 impl RegionSize {
+    /// Check address alignment
+    ///
+    /// Reports whether an address is aligned according to this region size
     pub fn is_aligned(&self, addr: *const u8) -> bool {
         let addr = addr as usize;
         if *self == RegionSize::_4G {
@@ -127,7 +130,7 @@ impl Drsr {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Drsr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/dspsr.rs b/aarch32-cpu/src/register/dspsr.rs
index ad5287b8..63d0af5a 100644
--- a/aarch32-cpu/src/register/dspsr.rs
+++ b/aarch32-cpu/src/register/dspsr.rs
@@ -22,7 +22,7 @@ impl Dspsr {
     #[inline]
     /// Reads DSPSR (*Debug Saved Program Status Register*)
     pub fn read() -> Dspsr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/fcseidr.rs b/aarch32-cpu/src/register/fcseidr.rs
index 1ad63f0a..713c17f6 100644
--- a/aarch32-cpu/src/register/fcseidr.rs
+++ b/aarch32-cpu/src/register/fcseidr.rs
@@ -22,7 +22,7 @@ impl Fcseidr {
     #[inline]
     /// Reads FCSEIDR (*FCSE Process ID Register*)
     pub fn read() -> Fcseidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cntfrq.rs b/aarch32-cpu/src/register/generic_timer/cntfrq.rs
index a29f903d..89ea1152 100644
--- a/aarch32-cpu/src/register/generic_timer/cntfrq.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntfrq.rs
@@ -22,7 +22,7 @@ impl Cntfrq {
     #[inline]
     /// Reads CNTFRQ (*Counter-timer Frequency Register*)
     pub fn read() -> Cntfrq {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cnthctl.rs b/aarch32-cpu/src/register/generic_timer/cnthctl.rs
index 3bbf894c..e4f646ca 100644
--- a/aarch32-cpu/src/register/generic_timer/cnthctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cnthctl.rs
@@ -8,40 +8,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Cnthctl {
-    #[bits(19..=19, rw)]
-    cntpmask: bool,
-    #[bits(18..=18, rw)]
-    cntvmask: bool,
-    #[bits(17..=17, rw)]
-    evntis: bool,
-    #[bits(16..=16, rw)]
-    el1nvvct: bool,
-    #[bits(15..=15, rw)]
-    el1nvpct: bool,
-    #[bits(14..=14, rw)]
-    el1tvct: bool,
-    #[bits(13..=13, rw)]
-    el1tvt: bool,
-    #[bits(12..=12, rw)]
-    ecv: bool,
-    #[bits(11..=11, rw)]
-    el1pten: bool,
-    #[bits(10..=10, rw)]
-    el1pcten: bool,
-    #[bits(9..=9, rw)]
-    el0pten: bool,
-    #[bits(8..=8, rw)]
-    el0vten: bool,
+    /// Selects which bit of CNTPCT, as seen from EL2, is the trigger for the
+    /// event stream generated from that counter when that stream is enabled.
     #[bits(4..=7, rw)]
     evnti: u4,
+    /// Controls which transition of the CNTPCT trigger bit, as seen from EL2
+    /// and defined by EVNTI, generates an event when the event stream is
+    /// enabled.
     #[bits(3..=3, rw)]
     evntdir: bool,
+    /// Enables the generation of an event stream from CNTPCT as seen from EL2.
     #[bits(2..=2, rw)]
     evnten: bool,
+    /// Traps Non-secure EL0 and EL1 MRC or MCR accesses, reported using EC
+    /// syndrome value 0x03, and MRRC or MCRR accesses, reported using EC
+    /// syndrome value 0x04, to the physical timer registers to Hyp mode.
     #[bits(1..=1, rw)]
-    el0vcten: bool,
+    pl1pcen: bool,
+    /// Traps Non-secure EL0 and EL1 MRRC or MCRR accesses, reported using EC
+    /// syndrome value 0x04, to the physical counter register to Hyp mode.
     #[bits(0..=0, rw)]
-    el0pcten: bool,
+    pl1pcten: bool,
 }
 
 impl SysReg for Cnthctl {
@@ -58,7 +45,7 @@ impl Cnthctl {
     #[inline]
     /// Reads CNTHCTL (*Hyp Counter-timer Control Register*)
     pub fn read() -> Cnthctl {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cnthp_ctl.rs b/aarch32-cpu/src/register/generic_timer/cnthp_ctl.rs
index 9dd3aa9e..79e57828 100644
--- a/aarch32-cpu/src/register/generic_timer/cnthp_ctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cnthp_ctl.rs
@@ -34,7 +34,7 @@ impl CnthpCtl {
     #[inline]
     /// Reads CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*)
     pub fn read() -> CnthpCtl {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cnthp_cval.rs b/aarch32-cpu/src/register/generic_timer/cnthp_cval.rs
index 32a38206..42789627 100644
--- a/aarch32-cpu/src/register/generic_timer/cnthp_cval.rs
+++ b/aarch32-cpu/src/register/generic_timer/cnthp_cval.rs
@@ -4,7 +4,7 @@ use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
 
 /// CNTHP_CVAL (*Hyp Physical Counter-timer CompareValue Register*)
 #[derive(Debug, Copy, Clone)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CnthpCval(pub u64);
 
@@ -20,7 +20,7 @@ impl CnthpCval {
     #[inline]
     /// Reads CNTHP_CVAL (*Hyp Physical Counter-timer CompareValue Register*)
     pub fn read() -> CnthpCval {
-        unsafe { Self(<Self as SysRegRead64>::read_raw()) }
+        Self(<Self as SysRegRead64>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cnthp_tval.rs b/aarch32-cpu/src/register/generic_timer/cnthp_tval.rs
index 09519a76..d1c4267e 100644
--- a/aarch32-cpu/src/register/generic_timer/cnthp_tval.rs
+++ b/aarch32-cpu/src/register/generic_timer/cnthp_tval.rs
@@ -22,7 +22,7 @@ impl CnthpTval {
     #[inline]
     /// Reads CNTHP_TVAL (*Hyp Physical Counter-timer TimerValue Register*)
     pub fn read() -> CnthpTval {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cntkctl.rs b/aarch32-cpu/src/register/generic_timer/cntkctl.rs
index 92db33f1..a9963b06 100644
--- a/aarch32-cpu/src/register/generic_timer/cntkctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntkctl.rs
@@ -68,7 +68,7 @@ impl Cntkctl {
     #[inline]
     /// Reads CNTKCTL (*Counter-timer Kernel Control Register*)
     pub fn read() -> Cntkctl {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cntp_ctl.rs b/aarch32-cpu/src/register/generic_timer/cntp_ctl.rs
index a61da3b9..ea2f8aa4 100644
--- a/aarch32-cpu/src/register/generic_timer/cntp_ctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntp_ctl.rs
@@ -44,7 +44,7 @@ impl CntpCtl {
     #[inline]
     /// Reads CNTP_CTL (*Physical Counter-timer Control Register*)
     pub fn read() -> CntpCtl {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cntp_cval.rs b/aarch32-cpu/src/register/generic_timer/cntp_cval.rs
index a71ba35c..7eb19bbc 100644
--- a/aarch32-cpu/src/register/generic_timer/cntp_cval.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntp_cval.rs
@@ -1,37 +1,37 @@
-//! Code for managing CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
-
-use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
-
-/// CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
-#[derive(Debug, Copy, Clone)]
+//! Code for managing CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
+
+use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
+
+/// CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
-pub struct CntpCval(pub u64);
-
-impl SysReg64 for CntpCval {
-    const CP: u32 = 15;
-    const OP1: u32 = 2;
-    const CRM: u32 = 14;
-}
-
-impl SysRegRead64 for CntpCval {}
-
-impl CntpCval {
-    #[inline]
-    /// Reads CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
-    pub fn read() -> CntpCval {
-        unsafe { Self(<Self as SysRegRead64>::read_raw()) }
-    }
-}
-
-impl SysRegWrite64 for CntpCval {}
-
-impl CntpCval {
-    #[inline]
-    /// Writes CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
-    pub fn write(value: Self) {
-        unsafe {
-            <Self as SysRegWrite64>::write_raw(value.0);
-        }
-    }
-}
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+pub struct CntpCval(pub u64);
+
+impl SysReg64 for CntpCval {
+    const CP: u32 = 15;
+    const OP1: u32 = 2;
+    const CRM: u32 = 14;
+}
+
+impl SysRegRead64 for CntpCval {}
+
+impl CntpCval {
+    #[inline]
+    /// Reads CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
+    pub fn read() -> CntpCval {
+        Self(<Self as SysRegRead64>::read_raw())
+    }
+}
+
+impl SysRegWrite64 for CntpCval {}
+
+impl CntpCval {
+    #[inline]
+    /// Writes CNTP_CVAL (*Physical Counter-timer CompareValue Register*)
+    pub fn write(value: Self) {
+        unsafe {
+            <Self as SysRegWrite64>::write_raw(value.0);
+        }
+    }
+}
diff --git a/aarch32-cpu/src/register/generic_timer/cntp_tval.rs b/aarch32-cpu/src/register/generic_timer/cntp_tval.rs
index ba255f07..457f99cc 100644
--- a/aarch32-cpu/src/register/generic_timer/cntp_tval.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntp_tval.rs
@@ -22,7 +22,7 @@ impl CntpTval {
     #[inline]
     /// Reads CNTP_TVAL (*Physical Counter-timer TimerValue Register*)
     pub fn read() -> CntpTval {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cntpct.rs b/aarch32-cpu/src/register/generic_timer/cntpct.rs
index 944c097e..278466bd 100644
--- a/aarch32-cpu/src/register/generic_timer/cntpct.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntpct.rs
@@ -20,6 +20,6 @@ impl CntPct {
     #[inline]
     /// Reads CNTPCT (*Physical Counter-timer Count Register*)
     pub fn read() -> CntPct {
-        unsafe { Self(<Self as SysRegRead64>::read_raw()) }
+        Self(<Self as SysRegRead64>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/generic_timer/cntv_ctl.rs b/aarch32-cpu/src/register/generic_timer/cntv_ctl.rs
index e7b4bc45..de4675ba 100644
--- a/aarch32-cpu/src/register/generic_timer/cntv_ctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntv_ctl.rs
@@ -44,7 +44,7 @@ impl CntvCtl {
     #[inline]
     /// Reads CNTV_CTL (*Virtual Counter-timer Control Register*)
     pub fn read() -> CntvCtl {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cntv_cval.rs b/aarch32-cpu/src/register/generic_timer/cntv_cval.rs
index ab605750..26983cf8 100644
--- a/aarch32-cpu/src/register/generic_timer/cntv_cval.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntv_cval.rs
@@ -20,7 +20,7 @@ impl CntvCval {
     #[inline]
     /// Reads CNTV_CVAL (*Virtual Counter-timer CompareValue Register*)
     pub fn read() -> CntvCval {
-        unsafe { Self(<Self as SysRegRead64>::read_raw()) }
+        Self(<Self as SysRegRead64>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cntv_tval.rs b/aarch32-cpu/src/register/generic_timer/cntv_tval.rs
index ba184f42..d2f87ea2 100644
--- a/aarch32-cpu/src/register/generic_timer/cntv_tval.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntv_tval.rs
@@ -22,7 +22,7 @@ impl CntvTval {
     #[inline]
     /// Reads CNTV_TVAL (*Virtual Counter-timer TimerValue Register*)
     pub fn read() -> CntvTval {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/generic_timer/cntvct.rs b/aarch32-cpu/src/register/generic_timer/cntvct.rs
index 36ea87b9..e039df02 100644
--- a/aarch32-cpu/src/register/generic_timer/cntvct.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntvct.rs
@@ -20,6 +20,6 @@ impl CntVct {
     #[inline]
     /// Reads CNTVCT (*Virtual Counter-timer Count Register*)
     pub fn read() -> CntVct {
-        unsafe { Self(<Self as SysRegRead64>::read_raw()) }
+        Self(<Self as SysRegRead64>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/generic_timer/cntvoff.rs b/aarch32-cpu/src/register/generic_timer/cntvoff.rs
index d019bb0c..6a4d2632 100644
--- a/aarch32-cpu/src/register/generic_timer/cntvoff.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntvoff.rs
@@ -4,7 +4,7 @@ use crate::register::{SysReg64, SysRegRead64, SysRegWrite64};
 
 /// CNTVOFF (*Virtual Counter-timer Offset Register*)
 #[derive(Debug, Copy, Clone)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntVoff(pub u64);
 
@@ -20,7 +20,7 @@ impl CntVoff {
     #[inline]
     /// Reads CNTVOFF (*Virtual Counter-timer Offset Register*)
     pub fn read() -> CntVoff {
-        unsafe { Self(<Self as SysRegRead64>::read_raw()) }
+        Self(<Self as SysRegRead64>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hacr.rs b/aarch32-cpu/src/register/hyp/hacr.rs
index 1690e9ca..ec8ff532 100644
--- a/aarch32-cpu/src/register/hyp/hacr.rs
+++ b/aarch32-cpu/src/register/hyp/hacr.rs
@@ -22,7 +22,7 @@ impl Hacr {
     #[inline]
     /// Reads HACR (*Hyp Auxiliary Configuration Register*)
     pub fn read() -> Hacr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hactlr.rs b/aarch32-cpu/src/register/hyp/hactlr.rs
index 8c88fb12..7cff5646 100644
--- a/aarch32-cpu/src/register/hyp/hactlr.rs
+++ b/aarch32-cpu/src/register/hyp/hactlr.rs
@@ -52,8 +52,7 @@ impl Hactlr {
     /// Read HACTRL (*Hyp Auxiliary Control Register*)
     #[inline]
     pub fn read() -> Hactlr {
-        // Safety: Reading this register has no side-effects and is atomic
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 
     /// Write HACTRL (*Hyp Auxiliary Control Register*)
diff --git a/aarch32-cpu/src/register/hyp/hactlr2.rs b/aarch32-cpu/src/register/hyp/hactlr2.rs
index 23cb4341..72a06f34 100644
--- a/aarch32-cpu/src/register/hyp/hactlr2.rs
+++ b/aarch32-cpu/src/register/hyp/hactlr2.rs
@@ -22,7 +22,7 @@ impl Hactlr2 {
     #[inline]
     /// Reads HACTLR2 (*Hyp Auxiliary Control Register 2*)
     pub fn read() -> Hactlr2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hadfsr.rs b/aarch32-cpu/src/register/hyp/hadfsr.rs
index c7041c04..cbbc83bb 100644
--- a/aarch32-cpu/src/register/hyp/hadfsr.rs
+++ b/aarch32-cpu/src/register/hyp/hadfsr.rs
@@ -22,7 +22,7 @@ impl Hadfsr {
     #[inline]
     /// Reads HADFSR (*Hyp Auxiliary Data Fault Status Register*)
     pub fn read() -> Hadfsr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/haifsr.rs b/aarch32-cpu/src/register/hyp/haifsr.rs
index e97b31fa..07b296e4 100644
--- a/aarch32-cpu/src/register/hyp/haifsr.rs
+++ b/aarch32-cpu/src/register/hyp/haifsr.rs
@@ -22,7 +22,7 @@ impl Haifsr {
     #[inline]
     /// Reads HAIFSR (*Hyp Auxiliary Instruction Fault Status Register*)
     pub fn read() -> Haifsr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hamair0.rs b/aarch32-cpu/src/register/hyp/hamair0.rs
index afa1300d..e3b39c29 100644
--- a/aarch32-cpu/src/register/hyp/hamair0.rs
+++ b/aarch32-cpu/src/register/hyp/hamair0.rs
@@ -22,7 +22,7 @@ impl Hamair0 {
     #[inline]
     /// Reads HAMAIR0 (*Hyp Auxiliary Memory Attribute Indirection Register 0*)
     pub fn read() -> Hamair0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hamair1.rs b/aarch32-cpu/src/register/hyp/hamair1.rs
index 4f8b6a18..835f2933 100644
--- a/aarch32-cpu/src/register/hyp/hamair1.rs
+++ b/aarch32-cpu/src/register/hyp/hamair1.rs
@@ -22,7 +22,7 @@ impl Hamair1 {
     #[inline]
     /// Reads HAMAIR1 (*Hyp Auxiliary Memory Attribute Indirection Register 1*)
     pub fn read() -> Hamair1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hcptr.rs b/aarch32-cpu/src/register/hyp/hcptr.rs
index 864adea7..436f1ceb 100644
--- a/aarch32-cpu/src/register/hyp/hcptr.rs
+++ b/aarch32-cpu/src/register/hyp/hcptr.rs
@@ -34,7 +34,7 @@ impl Hcptr {
     #[inline]
     /// Reads HCPTR (*Hyp Architectural Feature Trap Register*)
     pub fn read() -> Hcptr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 
     /// Modify HCPTR (*Hyp Architectural Feature Trap Register*)
diff --git a/aarch32-cpu/src/register/hyp/hcr.rs b/aarch32-cpu/src/register/hyp/hcr.rs
index 9424f92b..0f3b0864 100644
--- a/aarch32-cpu/src/register/hyp/hcr.rs
+++ b/aarch32-cpu/src/register/hyp/hcr.rs
@@ -98,9 +98,13 @@ pub struct Hcr {
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
 pub enum Bsu {
+    /// No effect
     NoEffect = 0b00,
+    /// Inner Shareable
     InnerShareable = 0b01,
+    /// Outer Shareable
     OuterShareable = 0b10,
+    /// Full System
     FullSystem = 0b11,
 }
 
@@ -118,7 +122,7 @@ impl Hcr {
     #[inline]
     /// Reads HCR (*Hyp Configuration Register*)
     pub fn read() -> Hcr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hcr2.rs b/aarch32-cpu/src/register/hyp/hcr2.rs
index 436873e3..b4e20e49 100644
--- a/aarch32-cpu/src/register/hyp/hcr2.rs
+++ b/aarch32-cpu/src/register/hyp/hcr2.rs
@@ -22,7 +22,7 @@ impl Hcr2 {
     #[inline]
     /// Reads HCR2 (*Hyp Configuration Register 2*)
     pub fn read() -> Hcr2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hdcr.rs b/aarch32-cpu/src/register/hyp/hdcr.rs
index 2fb31010..fe1b61f3 100644
--- a/aarch32-cpu/src/register/hyp/hdcr.rs
+++ b/aarch32-cpu/src/register/hyp/hdcr.rs
@@ -22,7 +22,7 @@ impl Hdcr {
     #[inline]
     /// Reads HDCR (*Hyp Debug Control Register*)
     pub fn read() -> Hdcr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hdfar.rs b/aarch32-cpu/src/register/hyp/hdfar.rs
index a6eff518..ec78f891 100644
--- a/aarch32-cpu/src/register/hyp/hdfar.rs
+++ b/aarch32-cpu/src/register/hyp/hdfar.rs
@@ -22,7 +22,7 @@ impl Hdfar {
     #[inline]
     /// Reads HDFAR (*Hyp Data Fault Address Register*)
     pub fn read() -> Hdfar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hifar.rs b/aarch32-cpu/src/register/hyp/hifar.rs
index ed385157..2866af35 100644
--- a/aarch32-cpu/src/register/hyp/hifar.rs
+++ b/aarch32-cpu/src/register/hyp/hifar.rs
@@ -22,7 +22,7 @@ impl Hifar {
     #[inline]
     /// Reads HIFAR (*Hyp Instruction Fault Address Register*)
     pub fn read() -> Hifar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hmair0.rs b/aarch32-cpu/src/register/hyp/hmair0.rs
index 3e217c43..c4cff925 100644
--- a/aarch32-cpu/src/register/hyp/hmair0.rs
+++ b/aarch32-cpu/src/register/hyp/hmair0.rs
@@ -22,7 +22,7 @@ impl Hmair0 {
     #[inline]
     /// Reads HMAIR0 (*Hyp Memory Attribute Indirection Register 0*)
     pub fn read() -> Hmair0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hmair1.rs b/aarch32-cpu/src/register/hyp/hmair1.rs
index 75febb28..4efbe6ad 100644
--- a/aarch32-cpu/src/register/hyp/hmair1.rs
+++ b/aarch32-cpu/src/register/hyp/hmair1.rs
@@ -22,7 +22,7 @@ impl Hmair1 {
     #[inline]
     /// Reads HMAIR1 (*Hyp Memory Attribute Indirection Register 1*)
     pub fn read() -> Hmair1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hpfar.rs b/aarch32-cpu/src/register/hyp/hpfar.rs
index 261004e8..8cfc49e7 100644
--- a/aarch32-cpu/src/register/hyp/hpfar.rs
+++ b/aarch32-cpu/src/register/hyp/hpfar.rs
@@ -23,7 +23,7 @@ impl Hpfar {
     #[inline]
     /// Reads HPFAR (*Hyp IPA Fault Address Register*)
     pub fn read() -> Hpfar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hsctlr.rs b/aarch32-cpu/src/register/hyp/hsctlr.rs
index b09e65e6..1c75d42b 100644
--- a/aarch32-cpu/src/register/hyp/hsctlr.rs
+++ b/aarch32-cpu/src/register/hyp/hsctlr.rs
@@ -57,7 +57,7 @@ impl Hsctlr {
     #[inline]
     /// Reads HSCTLR (*Hyp System Control Register*)
     pub fn read() -> Hsctlr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hsr.rs b/aarch32-cpu/src/register/hyp/hsr.rs
index b499db95..c6322902 100644
--- a/aarch32-cpu/src/register/hyp/hsr.rs
+++ b/aarch32-cpu/src/register/hyp/hsr.rs
@@ -42,24 +42,43 @@ impl Hsr {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
+/// Exception Class value from the HSR (*Hyp Syndrome Register*)
 pub enum ExceptionClass {
+    /// Unknown reason
     Unknown = 0b00_0000,
+    /// Trapped WFI or WFE instruction execution
     TrappedWfiWfe = 0b00_0001,
+    /// Trapped MCR or MRC access with (coproc==`0b1111`) that is not reported using EC value `0b000000``
     TrappedCp15McrMrc = 0b00_0011,
+    /// Trapped MCRR or MRRC access with (coproc==`0b1111`) that is not reported using EC value `0b000000``
     TrappedCp15McrrMrrc = 0b00_0100,
+    /// Trapped MCR or MRC access with (coproc==`0b1110``)
     TrappedCp14McrMrc = 0b00_0101,
+    /// Trapped LDC or STC access
     TrappedLdcStc = 0b00_0110,
+    /// Access to Advanced SIMD or floating-point functionality trapped by a `HCPTR.{TASE, TCP10}` control
     TrappedFpu = 0b00_0111,
+    /// Trapped VMRS access, from ID group trap, that is not reported using EC value `0b000111`
     TrappedVmrs = 0b00_1000,
+    /// Trapped MRRC access with (coproc==`0b1110`)
     TrappedCp14McrrMrrc = 0b00_1100,
+    /// Illegal exception return to AArch32 state
     IllegalAArch32Eret = 0b00_1110,
+    /// Exception on SVC instruction execution in AArch32 state routed to EL2
     Svc = 0b01_0001,
+    /// HVC instruction execution in AArch32 state, when HVC is not disabled
     Hvc = 0b01_0010,
+    /// Trapped execution of SMC instruction in AArch32 state
     Smc = 0b01_0011,
+    /// Prefetch Abort from a lower Exception level
     PrefetchAbortFromLower = 0b10_0000,
+    /// Prefetch Abort taken without a change in Exception level
     PrefetchAbortFromCurrent = 0b10_0001,
+    /// PC alignment fault exception
     PcAlignment = 0b10_0010,
+    /// Data Abort exception from a lower Exception level
     DataAbortFromLower = 0b10_0100,
+    /// Data Abort exception taken without a change in Exception level
     DataAbortFromCurrent = 0b10_0101,
 }
 
@@ -68,27 +87,46 @@ pub enum ExceptionClass {
 /// ISS is a 25 bit field whose meaning varies depending on the value of the EC field.
 #[derive(Debug, Clone)]
 pub enum Iss {
+    /// ISS for [`ExceptionClass::Unknown`]
     Unknown(IssUnknown),
+    /// ISS for [`ExceptionClass::TrappedWfiWfe`]
     TrappedWfiWfe(IssTrappedWfiWfe),
+    /// ISS for [`ExceptionClass::TrappedCp15McrMrc`]
     TrappedCp15McrMrc(IssTrappedMcrMrc),
+    /// ISS for [`ExceptionClass::TrappedCp15McrrMrrc`]
     TrappedCp15McrrMrrc(IssTrappedMcrrMrrc),
+    /// ISS for [`ExceptionClass::TrappedCp14McrMrc`]
     TrappedCp14McrMrc(IssTrappedMcrMrc),
+    /// ISS for [`ExceptionClass::TrappedLdcStc`]
     TrappedLdcStc(IssTrappedLdcStc),
+    /// ISS for [`ExceptionClass::TrappedFpu`]
     TrappedFpu(IssTrappedFpu),
+    /// ISS for [`ExceptionClass::TrappedVmrs`]
     TrappedVmrs(IssTrappedVmrs),
+    /// ISS for [`ExceptionClass::TrappedCp14McrrMrrc`]
     TrappedCp14McrrMrrc(IssTrappedMcrrMrrc),
+    /// ISS for [`ExceptionClass::IllegalAArch32Eret`]
     IllegalAArch32Eret,
+    /// ISS for [`ExceptionClass::Svc`]
     Svc(IssCall),
+    /// ISS for [`ExceptionClass::Hvc`]
     Hvc(IssCall),
+    /// ISS for [`ExceptionClass::Smc`]
     Smc(IssSmc),
+    /// ISS for [`ExceptionClass::PrefetchAbortFromLower`]
     PrefetchAbortFromLower(IssPrefetchAbort),
+    /// ISS for [`ExceptionClass::PrefetchAbortFromCurrent`]
     PrefetchAbortFromCurrent(IssPrefetchAbort),
+    /// ISS for [`ExceptionClass::PcAlignment`]
     PcAlignment,
+    /// ISS for [`ExceptionClass::DataAbortFromLower`]
     DataAbortFromLower(IssDataAbort),
+    /// ISS for [`ExceptionClass::DataAbortFromCurrent`]
     DataAbortFromCurrent(IssDataAbort),
 }
 
 impl ExceptionClass {
+    /// Convert an ISS value based on the Exception Class
     pub fn decode_iss(&self, iss: u25) -> Iss {
         match self {
             ExceptionClass::Unknown => Iss::Unknown(IssUnknown(iss.value())),
@@ -324,8 +362,11 @@ pub struct IssDataAbort {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
+/// The length of the instruction that trapped
 pub enum InstructionLength {
+    /// A 16-bit instruction
     SixteenBit = 0b0,
+    /// A 32-bit instruction
     ThirtyTwoBit = 0b1,
 }
 
@@ -343,7 +384,7 @@ impl Hsr {
     #[inline]
     /// Reads HSR (*Hyp Syndrome Register*)
     pub fn read() -> Hsr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hstr.rs b/aarch32-cpu/src/register/hyp/hstr.rs
index 331f1360..6bd4e7c8 100644
--- a/aarch32-cpu/src/register/hyp/hstr.rs
+++ b/aarch32-cpu/src/register/hyp/hstr.rs
@@ -22,7 +22,7 @@ impl Hstr {
     #[inline]
     /// Reads HSTR (*Hyp System Trap Register*)
     pub fn read() -> Hstr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/htpidr.rs b/aarch32-cpu/src/register/hyp/htpidr.rs
index 7534bf0d..50d9028e 100644
--- a/aarch32-cpu/src/register/hyp/htpidr.rs
+++ b/aarch32-cpu/src/register/hyp/htpidr.rs
@@ -22,7 +22,7 @@ impl Htpidr {
     #[inline]
     /// Reads HTPIDR (*Hyp Software Thread ID Register*)
     pub fn read() -> Htpidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/hyp/hvbar.rs b/aarch32-cpu/src/register/hyp/hvbar.rs
index 13e238c5..4cbc6c0a 100644
--- a/aarch32-cpu/src/register/hyp/hvbar.rs
+++ b/aarch32-cpu/src/register/hyp/hvbar.rs
@@ -1,4 +1,4 @@
-//! Code for HVBAR (*Hyp Vector Base Address Register*)
+//! Code for managing HVBAR (*Hyp Vector Base Address Register*)
 
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
@@ -29,8 +29,7 @@ impl Hvbar {
     /// Read HVBAR (*Hyp Vector Base Address Register*)
     #[inline]
     pub fn read() -> Hvbar {
-        // Safety: Reading this register has no side-effects and is atomic
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 
     /// Write HVBAR (*Hyp Vector Base Address Register*)
diff --git a/aarch32-cpu/src/register/icc_pmr.rs b/aarch32-cpu/src/register/icc_pmr.rs
index 7e5c77b4..6fb17d10 100644
--- a/aarch32-cpu/src/register/icc_pmr.rs
+++ b/aarch32-cpu/src/register/icc_pmr.rs
@@ -22,7 +22,7 @@ impl IccPmr {
     #[inline]
     /// Reads ICC_PMR (*Interrupt Controller Interrupt Priority Mask Register*)
     pub fn read() -> IccPmr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/iciallu.rs b/aarch32-cpu/src/register/iciallu.rs
index 589bd949..a0c1d552 100644
--- a/aarch32-cpu/src/register/iciallu.rs
+++ b/aarch32-cpu/src/register/iciallu.rs
@@ -1,4 +1,4 @@
-//! Code for managing ICIALLU (*Invalidate all instruction caches to PoU.*)
+//! Code for managing ICIALLU (*Invalidate entire instruction cache to PoU Register*)
 //!
 //! Starting with ARMv6, the type of cache can be determined from the System Coprocessor register 0,
 //! and controlled through registers 1, 7 and 9. In earlier architecture variants, it is
@@ -8,6 +8,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// ICIALLU (*Invalidate entire instruction cache to PoU Register*)
 pub struct Iciallu;
 
 impl SysReg for Iciallu {
@@ -22,7 +23,7 @@ impl crate::register::SysRegWrite for Iciallu {}
 
 impl Iciallu {
     #[inline]
-    /// Writes ICIALLU (*Invalidate all instruction caches to PoU.*)
+    /// Writes 0 to ICIALLU (*Invalidate entire instruction cache to PoU Register*) to trigger operation
     pub fn write() {
         unsafe {
             <Self as SysRegWrite>::write_raw(0);
diff --git a/aarch32-cpu/src/register/id_afr0.rs b/aarch32-cpu/src/register/id_afr0.rs
index 54fbf320..67dd1549 100644
--- a/aarch32-cpu/src/register/id_afr0.rs
+++ b/aarch32-cpu/src/register/id_afr0.rs
@@ -22,6 +22,6 @@ impl IdAfr0 {
     #[inline]
     /// Reads ID_AFR0 (*Auxiliary Feature Register 0*)
     pub fn read() -> IdAfr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_dfr0.rs b/aarch32-cpu/src/register/id_dfr0.rs
index c19b0e4e..c621e2fd 100644
--- a/aarch32-cpu/src/register/id_dfr0.rs
+++ b/aarch32-cpu/src/register/id_dfr0.rs
@@ -22,6 +22,6 @@ impl IdDfr0 {
     #[inline]
     /// Reads ID_DFR0 (*Debug Feature Register 0*)
     pub fn read() -> IdDfr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_isar0.rs b/aarch32-cpu/src/register/id_isar0.rs
index 63cf8851..cbbd647b 100644
--- a/aarch32-cpu/src/register/id_isar0.rs
+++ b/aarch32-cpu/src/register/id_isar0.rs
@@ -22,6 +22,6 @@ impl IdIsar0 {
     #[inline]
     /// Reads ID_ISAR0 (*Instruction Set Attribute Register 0*)
     pub fn read() -> IdIsar0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_isar1.rs b/aarch32-cpu/src/register/id_isar1.rs
index 4fdce861..1cc642e7 100644
--- a/aarch32-cpu/src/register/id_isar1.rs
+++ b/aarch32-cpu/src/register/id_isar1.rs
@@ -22,6 +22,6 @@ impl IdIsar1 {
     #[inline]
     /// Reads ID_ISAR1 (*Instruction Set Attribute Register 1*)
     pub fn read() -> IdIsar1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_isar2.rs b/aarch32-cpu/src/register/id_isar2.rs
index 84b9d0a2..1f77e359 100644
--- a/aarch32-cpu/src/register/id_isar2.rs
+++ b/aarch32-cpu/src/register/id_isar2.rs
@@ -22,6 +22,6 @@ impl IdIsar2 {
     #[inline]
     /// Reads ID_ISAR2 (*Instruction Set Attribute Register 2*)
     pub fn read() -> IdIsar2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_isar3.rs b/aarch32-cpu/src/register/id_isar3.rs
index 66764315..b3e892c5 100644
--- a/aarch32-cpu/src/register/id_isar3.rs
+++ b/aarch32-cpu/src/register/id_isar3.rs
@@ -22,6 +22,6 @@ impl IdIsar3 {
     #[inline]
     /// Reads ID_ISAR3 (*Instruction Set Attribute Register 3*)
     pub fn read() -> IdIsar3 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_isar4.rs b/aarch32-cpu/src/register/id_isar4.rs
index 8d2cab9f..bace65cd 100644
--- a/aarch32-cpu/src/register/id_isar4.rs
+++ b/aarch32-cpu/src/register/id_isar4.rs
@@ -22,6 +22,6 @@ impl IdIsar4 {
     #[inline]
     /// Reads ID_ISAR4 (*Instruction Set Attribute Register 4*)
     pub fn read() -> IdIsar4 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_isar5.rs b/aarch32-cpu/src/register/id_isar5.rs
index ed6540d8..9de8a584 100644
--- a/aarch32-cpu/src/register/id_isar5.rs
+++ b/aarch32-cpu/src/register/id_isar5.rs
@@ -22,6 +22,6 @@ impl IdIsar5 {
     #[inline]
     /// Reads ID_ISAR5 (*Instruction Set Attribute Register 5*)
     pub fn read() -> IdIsar5 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_mmfr0.rs b/aarch32-cpu/src/register/id_mmfr0.rs
index fd9d3c2e..b7a814ef 100644
--- a/aarch32-cpu/src/register/id_mmfr0.rs
+++ b/aarch32-cpu/src/register/id_mmfr0.rs
@@ -22,6 +22,6 @@ impl IdMmfr0 {
     #[inline]
     /// Reads ID_MMFR0 (*Memory Model Feature Register 0*)
     pub fn read() -> IdMmfr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_mmfr1.rs b/aarch32-cpu/src/register/id_mmfr1.rs
index 6ebd0ec8..3ca8868c 100644
--- a/aarch32-cpu/src/register/id_mmfr1.rs
+++ b/aarch32-cpu/src/register/id_mmfr1.rs
@@ -22,6 +22,6 @@ impl IdMmfr1 {
     #[inline]
     /// Reads ID_MMFR1 (*Memory Model Feature Register 1*)
     pub fn read() -> IdMmfr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_mmfr2.rs b/aarch32-cpu/src/register/id_mmfr2.rs
index e71fb8b0..b7045792 100644
--- a/aarch32-cpu/src/register/id_mmfr2.rs
+++ b/aarch32-cpu/src/register/id_mmfr2.rs
@@ -22,6 +22,6 @@ impl IdMmfr2 {
     #[inline]
     /// Reads ID_MMFR2 (*Memory Model Feature Register 2*)
     pub fn read() -> IdMmfr2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_mmfr3.rs b/aarch32-cpu/src/register/id_mmfr3.rs
index 4fe042af..0718e0b5 100644
--- a/aarch32-cpu/src/register/id_mmfr3.rs
+++ b/aarch32-cpu/src/register/id_mmfr3.rs
@@ -22,6 +22,6 @@ impl IdMmfr3 {
     #[inline]
     /// Reads ID_MMFR3 (*Memory Model Feature Register 3*)
     pub fn read() -> IdMmfr3 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_mmfr4.rs b/aarch32-cpu/src/register/id_mmfr4.rs
index a4d101f2..74e645ac 100644
--- a/aarch32-cpu/src/register/id_mmfr4.rs
+++ b/aarch32-cpu/src/register/id_mmfr4.rs
@@ -22,6 +22,6 @@ impl IdMmfr4 {
     #[inline]
     /// Reads ID_MMFR4 (*Memory Model Feature Register 4*)
     pub fn read() -> IdMmfr4 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_pfr0.rs b/aarch32-cpu/src/register/id_pfr0.rs
index 06435711..f93f2830 100644
--- a/aarch32-cpu/src/register/id_pfr0.rs
+++ b/aarch32-cpu/src/register/id_pfr0.rs
@@ -22,6 +22,6 @@ impl IdPfr0 {
     #[inline]
     /// Reads ID_PFR0 (*Processor Feature Register 0*)
     pub fn read() -> IdPfr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/id_pfr1.rs b/aarch32-cpu/src/register/id_pfr1.rs
index f3bea178..91accc91 100644
--- a/aarch32-cpu/src/register/id_pfr1.rs
+++ b/aarch32-cpu/src/register/id_pfr1.rs
@@ -22,6 +22,6 @@ impl IdPfr1 {
     #[inline]
     /// Reads ID_PFR1 (*Processor Feature Register 1*)
     pub fn read() -> IdPfr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/ifar.rs b/aarch32-cpu/src/register/ifar.rs
index b2cfa875..71d93c15 100644
--- a/aarch32-cpu/src/register/ifar.rs
+++ b/aarch32-cpu/src/register/ifar.rs
@@ -22,7 +22,7 @@ impl Ifar {
     #[inline]
     /// Reads IFAR (*Instruction Fault Address Register*)
     pub fn read() -> Ifar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/ifsr.rs b/aarch32-cpu/src/register/ifsr.rs
index 00efa8d7..237a1051 100644
--- a/aarch32-cpu/src/register/ifsr.rs
+++ b/aarch32-cpu/src/register/ifsr.rs
@@ -86,18 +86,31 @@ pub struct Ifsr {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v5te")]
 pub enum IfsrStatus {
+    /// PC Alignment Fault
     Alignment = 1,
+    /// Debug Exception
     DebugEvent = 2,
+    /// Alternate value for PC Alignment Fault
     AlignmentAlt = 3,
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 5,
+    /// Translation fault, level 2
     TranslationFaultSecondLevel = 7,
+    /// Synchronous External abort
     SyncExtAbort = 8,
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 9,
+    /// Alternate value for Synchronous External abort
     SyncExtAbortAlt = 10,
+    /// Domain fault, level 2
     DomainFaultSecondLevel = 11,
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 13,
+    /// Synchronous External abort, on translation table walk, level 2
     SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
+    /// Permission fault, level 2
     PermissionFaultSecondLevel = 15,
 }
 
@@ -108,18 +121,31 @@ pub enum IfsrStatus {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v6")]
 pub enum IfsrStatus {
+    /// PC Alignment Fault
     Alignment = 1,
+    /// Debug Exception
     DebugEvent = 2,
+    /// Access Flag fault, level 1
     AccessFlagFaultFirstLevel = 3,
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 5,
+    /// Access Flag fault, level 2
     AccessFlagFaultSecondLevel = 6,
+    /// Translation fault, level 2
     TranslationFaultSecondLevel = 7,
+    /// Synchronouse External Abort
     SyncExtAbort = 8,
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 9,
+    /// Domain fault, level 2
     DomainFaultSecondLevel = 11,
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 13,
+    /// Synchronous External abort, on translation table walk, level 2
     SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
+    /// Permission fault, level 2
     PermissionFaultSecondLevel = 15,
 }
 
@@ -130,12 +156,19 @@ pub enum IfsrStatus {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v7-r")]
 pub enum IfsrStatus {
+    /// PC Alignment Fault
     Alignment = 1,
+    /// Debug Exception
     DebugEvent = 2,
+    /// Synchronous External abort
     SyncExtAbort = 8,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 13,
+    /// Asynchronous External abort
     AsyncExtAbort = 21,
+    /// Synchronous parity or ECC error
     SyncParityEccError = 25,
+    /// asynchronous parity or ECC error
     AsyncParityEccError = 24,
 }
 
@@ -146,23 +179,41 @@ pub enum IfsrStatus {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v7-a")]
 pub enum IfsrStatus {
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 0b01100,
+    /// Synchronous External abort, on translation table walk, level 2
     SyncExtAbortOnTranslationTableWalkSecondLevel = 0b01110,
+    /// Synchronous parity or ECC error on memory access, on translation table walk, level 1
     SyncParErrorOnTranslationTableWalkFirstLevel = 0b11100,
+    /// Synchronous parity or ECC error on memory access, on translation table walk, level 2
     SyncParErrorOnTranslationTableWalkSecondLevel = 0b11110,
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 0b00101,
+    /// Translation fault, level 2
     TranslationFaultSecondLevel = 0b00111,
+    /// Access flag fault, level 1
     AccessFlagFaultFirstLevel = 0b00011,
+    /// Access flag fault, level 2
     AccessFlagFaultSecondLevel = 0b00110,
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 0b01001,
+    /// Domain fault, level 2
     DomainFaultSecondLevel = 0b01011,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 0b01101,
+    /// Permission fault, level 2
     PermissionFaultSecondLevel = 0b01111,
+    /// Debug exception
     DebugEvent = 0b00010,
+    /// Synchronous External abort
     SyncExtAbort = 0b01000,
+    /// TLB conflict abort
     TlbConflictAbort = 0b10000,
+    /// IMPLEMENTATION DEFINED fault (Lockdown fault)
     Lockdown = 0b10100,
+    /// Co-Processor Abort
     CoprocessorAbort = 0b11010,
+    /// Synchronous parity or ECC error on memory access, not on translation table walk
     SyncParErrorOnMemAccess = 0b11001,
 }
 
@@ -173,11 +224,17 @@ pub enum IfsrStatus {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v8-r")]
 pub enum IfsrStatus {
+    /// Translation fault
     Translation = 4,
+    /// Permission fault
     Permission = 12,
+    /// Synchronous External abort
     SyncExtAbort = 16,
+    /// Synchronous parity or ECC error on memory access
     SyncParityEccError = 24,
+    /// PC alignment fault
     PcAlignment = 33,
+    /// Debug exception
     Debug = 34,
 }
 
@@ -195,7 +252,7 @@ impl Ifsr {
     #[inline]
     /// Reads IFSR (*Instruction Fault Status Register*)
     pub fn read() -> Ifsr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_atcmregionr.rs b/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
index d64b6bf5..8f962958 100644
--- a/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
@@ -22,7 +22,7 @@ impl ImpAtcmregionr {
     #[inline]
     /// Reads IMP_ATCMREGIONR (*TCM Region Registers A B and C*)
     pub fn read() -> ImpAtcmregionr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_bpctlr.rs b/aarch32-cpu/src/register/imp/imp_bpctlr.rs
index 4f1a2826..c8af2ace 100644
--- a/aarch32-cpu/src/register/imp/imp_bpctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_bpctlr.rs
@@ -22,7 +22,7 @@ impl ImpBpctlr {
     #[inline]
     /// Reads IMP_BPCTLR (*Branch Predictor Control Register*)
     pub fn read() -> ImpBpctlr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_btcmregionr.rs b/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
index 60dccb0f..2428fe95 100644
--- a/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
@@ -22,7 +22,7 @@ impl ImpBtcmregionr {
     #[inline]
     /// Reads IMP_BTCMREGIONR (*TCM Region Registers A B and C*)
     pub fn read() -> ImpBtcmregionr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_buildoptr.rs b/aarch32-cpu/src/register/imp/imp_buildoptr.rs
index 6b173d71..16326c89 100644
--- a/aarch32-cpu/src/register/imp/imp_buildoptr.rs
+++ b/aarch32-cpu/src/register/imp/imp_buildoptr.rs
@@ -22,6 +22,6 @@ impl ImpBuildoptr {
     #[inline]
     /// Reads IMP_BUILDOPTR (*Build Options Register*)
     pub fn read() -> ImpBuildoptr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs b/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
index 2fe9b22d..1ef94da9 100644
--- a/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
+++ b/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
@@ -22,7 +22,7 @@ impl ImpBustimeoutr {
     #[inline]
     /// Reads IMP_BUSTIMEOUTR (*Bus Timeout Register*)
     pub fn read() -> ImpBustimeoutr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_cbar.rs b/aarch32-cpu/src/register/imp/imp_cbar.rs
index 0d0384f3..c09ded8c 100644
--- a/aarch32-cpu/src/register/imp/imp_cbar.rs
+++ b/aarch32-cpu/src/register/imp/imp_cbar.rs
@@ -21,8 +21,7 @@ impl ImpCbar {
     /// Read IMP_CBAR (*Configuration Base Address Register*)
     #[inline]
     pub fn read() -> ImpCbar {
-        // Safety: this read has no side-effects
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 
     /// Get the periphbase address
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs b/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
index 9abc129a..fbbb8e15 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDCD (*Data Cache Data Read Operation.*)
+//! Code for managing IMP_CDBGDCD (*Data Cache Data Read Operation*)
 
 use crate::register::{SysReg, SysRegWrite};
 
-/// IMP_CDBGDCD (*Data Cache Data Read Operation.*)
+/// IMP_CDBGDCD (*Data Cache Data Read Operation*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -20,7 +20,7 @@ impl crate::register::SysRegWrite for ImpCdbgdcd {}
 
 impl ImpCdbgdcd {
     #[inline]
-    /// Writes IMP_CDBGDCD (*Data Cache Data Read Operation.*)
+    /// Writes IMP_CDBGDCD (*Data Cache Data Read Operation*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdct.rs b/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
index 00194b37..5933a5ae 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDCT (*Data Cache Tag Read Operation.*)
+//! Code for managing IMP_CDBGDCT (*Data Cache Tag Read Operation*)
 
 use crate::register::{SysReg, SysRegWrite};
 
-/// IMP_CDBGDCT (*Data Cache Tag Read Operation.*)
+/// IMP_CDBGDCT (*Data Cache Tag Read Operation*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -20,7 +20,7 @@ impl crate::register::SysRegWrite for ImpCdbgdct {}
 
 impl ImpCdbgdct {
     #[inline]
-    /// Writes IMP_CDBGDCT (*Data Cache Tag Read Operation.*)
+    /// Writes IMP_CDBGDCT (*Data Cache Tag Read Operation*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
index 1d3e87b7..fdaa4f87 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDR0 (*Cache Debug Data Register 0.*)
+//! Code for managing IMP_CDBGDR0 (*Cache Debug Data Register 0*)
 
 use crate::register::{SysReg, SysRegRead};
 
-/// IMP_CDBGDR0 (*Cache Debug Data Register 0.*)
+/// IMP_CDBGDR0 (*Cache Debug Data Register 0*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -20,8 +20,8 @@ impl crate::register::SysRegRead for ImpCdbgdr0 {}
 
 impl ImpCdbgdr0 {
     #[inline]
-    /// Reads IMP_CDBGDR0 (*Cache Debug Data Register 0.*)
+    /// Reads IMP_CDBGDR0 (*Cache Debug Data Register 0*)
     pub fn read() -> ImpCdbgdr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
index 128919dd..f7da47bc 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDR1 (*Cache Debug Data Register 1.*)
+//! Code for managing IMP_CDBGDR1 (*Cache Debug Data Register 1*)
 
 use crate::register::{SysReg, SysRegRead};
 
-/// IMP_CDBGDR1 (*Cache Debug Data Register 1.*)
+/// IMP_CDBGDR1 (*Cache Debug Data Register 1*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -20,8 +20,8 @@ impl crate::register::SysRegRead for ImpCdbgdr1 {}
 
 impl ImpCdbgdr1 {
     #[inline]
-    /// Reads IMP_CDBGDR1 (*Cache Debug Data Register 1.*)
+    /// Reads IMP_CDBGDR1 (*Cache Debug Data Register 1*)
     pub fn read() -> ImpCdbgdr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
index 4fc3e103..a6b3d927 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDR2 (*Cache Debug Data Register 2.*)
+//! Code for managing IMP_CDBGDR2 (*Cache Debug Data Register 2*)
 
 use crate::register::{SysReg, SysRegRead};
 
-/// IMP_CDBGDR2 (*Cache Debug Data Register 2.*)
+/// IMP_CDBGDR2 (*Cache Debug Data Register 2*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -20,8 +20,8 @@ impl crate::register::SysRegRead for ImpCdbgdr2 {}
 
 impl ImpCdbgdr2 {
     #[inline]
-    /// Reads IMP_CDBGDR2 (*Cache Debug Data Register 2.*)
+    /// Reads IMP_CDBGDR2 (*Cache Debug Data Register 2*)
     pub fn read() -> ImpCdbgdr2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgicd.rs b/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
index 9847be2b..64d5705f 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGICD (*Instruction Cache Data Read Operation.*)
+//! Code for managing IMP_CDBGICD (*Instruction Cache Data Read Operation*)
 
 use crate::register::{SysReg, SysRegWrite};
 
-/// IMP_CDBGICD (*Instruction Cache Data Read Operation.*)
+/// IMP_CDBGICD (*Instruction Cache Data Read Operation*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -20,7 +20,7 @@ impl crate::register::SysRegWrite for ImpCdbgicd {}
 
 impl ImpCdbgicd {
     #[inline]
-    /// Writes IMP_CDBGICD (*Instruction Cache Data Read Operation.*)
+    /// Writes IMP_CDBGICD (*Instruction Cache Data Read Operation*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgict.rs b/aarch32-cpu/src/register/imp/imp_cdbgict.rs
index cab5cec1..f6c847b4 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgict.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgict.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGICT (*Instruction Cache Tag Read Operation.*)
+//! Code for managing IMP_CDBGICT (*Instruction Cache Tag Read Operation*)
 
 use crate::register::{SysReg, SysRegWrite};
 
-/// IMP_CDBGICT (*Instruction Cache Tag Read Operation.*)
+/// IMP_CDBGICT (*Instruction Cache Tag Read Operation*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -20,7 +20,7 @@ impl crate::register::SysRegWrite for ImpCdbgict {}
 
 impl ImpCdbgict {
     #[inline]
-    /// Writes IMP_CDBGICT (*Instruction Cache Tag Read Operation.*)
+    /// Writes IMP_CDBGICT (*Instruction Cache Tag Read Operation*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/imp/imp_csctlr.rs b/aarch32-cpu/src/register/imp/imp_csctlr.rs
index aa0d8d9e..7b60ad42 100644
--- a/aarch32-cpu/src/register/imp/imp_csctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_csctlr.rs
@@ -22,7 +22,7 @@ impl ImpCsctlr {
     #[inline]
     /// Reads IMP_CSCTLR (*Cache Segregation Control Register*)
     pub fn read() -> ImpCsctlr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs b/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
index 6674163c..59a5c92d 100644
--- a/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
@@ -22,7 +22,7 @@ impl ImpCtcmregionr {
     #[inline]
     /// Reads IMP_CTCMREGIONR (*TCM Region Registers A B and C*)
     pub fn read() -> ImpCtcmregionr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_dcerr0.rs b/aarch32-cpu/src/register/imp/imp_dcerr0.rs
index 1ef40da1..ef444fe5 100644
--- a/aarch32-cpu/src/register/imp/imp_dcerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_dcerr0.rs
@@ -22,7 +22,7 @@ impl ImpDcerr0 {
     #[inline]
     /// Reads IMP_DCERR0 (*Data Cache Error Record Register 0*)
     pub fn read() -> ImpDcerr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_dcerr1.rs b/aarch32-cpu/src/register/imp/imp_dcerr1.rs
index 07b9e5cc..902c2228 100644
--- a/aarch32-cpu/src/register/imp/imp_dcerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_dcerr1.rs
@@ -22,7 +22,7 @@ impl ImpDcerr1 {
     #[inline]
     /// Reads DMP_ICERR1 (*Data Cache Error Record Register 1*)
     pub fn read() -> ImpDcerr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_flasherr0.rs b/aarch32-cpu/src/register/imp/imp_flasherr0.rs
index ebdea8d9..f5414713 100644
--- a/aarch32-cpu/src/register/imp/imp_flasherr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_flasherr0.rs
@@ -22,7 +22,7 @@ impl ImpFlasherr0 {
     #[inline]
     /// Reads IMP_FLASHERR0 (*Flash Error Record Register 0*)
     pub fn read() -> ImpFlasherr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_flasherr1.rs b/aarch32-cpu/src/register/imp/imp_flasherr1.rs
index 1fe83787..618960b6 100644
--- a/aarch32-cpu/src/register/imp/imp_flasherr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_flasherr1.rs
@@ -22,7 +22,7 @@ impl ImpFlasherr1 {
     #[inline]
     /// Reads IMP_FLASHERR1 (*Flash Error Record Register 1*)
     pub fn read() -> ImpFlasherr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_flashifregionr.rs b/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
index 8b9290e0..76adbed2 100644
--- a/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
@@ -22,7 +22,7 @@ impl ImpFlashifregionr {
     #[inline]
     /// Reads IMP_FLASHIFREGIONR (*Flash Interface Region Register*)
     pub fn read() -> ImpFlashifregionr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_icerr0.rs b/aarch32-cpu/src/register/imp/imp_icerr0.rs
index cdfb24fa..9846b675 100644
--- a/aarch32-cpu/src/register/imp/imp_icerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_icerr0.rs
@@ -22,7 +22,7 @@ impl ImpIcerr0 {
     #[inline]
     /// Reads IMP_ICERR0 (*Instruction Cache Error Record Register 0*)
     pub fn read() -> ImpIcerr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_icerr1.rs b/aarch32-cpu/src/register/imp/imp_icerr1.rs
index 12da076c..676c615c 100644
--- a/aarch32-cpu/src/register/imp/imp_icerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_icerr1.rs
@@ -22,7 +22,7 @@ impl ImpIcerr1 {
     #[inline]
     /// Reads IMP_ICERR1 (*Instruction Cache Error Record Register 1*)
     pub fn read() -> ImpIcerr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_intmonr.rs b/aarch32-cpu/src/register/imp/imp_intmonr.rs
index 86315ab8..b41744b9 100644
--- a/aarch32-cpu/src/register/imp/imp_intmonr.rs
+++ b/aarch32-cpu/src/register/imp/imp_intmonr.rs
@@ -22,7 +22,7 @@ impl ImpIntmonr {
     #[inline]
     /// Reads IMP_INTMONR (*Interrupt Monitoring Register*)
     pub fn read() -> ImpIntmonr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_memprotctlr.rs b/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
index 14960247..9d8a21ff 100644
--- a/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
@@ -22,7 +22,7 @@ impl ImpMemprotctlr {
     #[inline]
     /// Reads IMP_MEMPROTCTLR (*Memory Protection Control Register*)
     pub fn read() -> ImpMemprotctlr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_periphpregionr.rs b/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
index 51643758..ad841a12 100644
--- a/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
@@ -22,7 +22,7 @@ impl ImpPeriphpregionr {
     #[inline]
     /// Reads IMP_PERIPHPREGIONR (*Peripheral Port Region Register*)
     pub fn read() -> ImpPeriphpregionr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_pinoptr.rs b/aarch32-cpu/src/register/imp/imp_pinoptr.rs
index e2b7b6ad..c02745f0 100644
--- a/aarch32-cpu/src/register/imp/imp_pinoptr.rs
+++ b/aarch32-cpu/src/register/imp/imp_pinoptr.rs
@@ -22,6 +22,6 @@ impl ImpPinoptr {
     #[inline]
     /// Reads IMP_PINOPTR (*Pin Options Register*)
     pub fn read() -> ImpPinoptr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/imp/imp_qosr.rs b/aarch32-cpu/src/register/imp/imp_qosr.rs
index d8e74e75..0667171e 100644
--- a/aarch32-cpu/src/register/imp/imp_qosr.rs
+++ b/aarch32-cpu/src/register/imp/imp_qosr.rs
@@ -22,7 +22,7 @@ impl ImpQosr {
     #[inline]
     /// Reads IMP_QOSR (*Quality Of Service Register*)
     pub fn read() -> ImpQosr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_slavepctlr.rs b/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
index f259a0d1..6b941e20 100644
--- a/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
@@ -22,7 +22,7 @@ impl ImpSlavepctlr {
     #[inline]
     /// Reads IMP_SLAVEPCTLR (*Slave Port Control Register*)
     pub fn read() -> ImpSlavepctlr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_tcmerr0.rs b/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
index b98ccad4..f3ff733d 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
@@ -22,7 +22,7 @@ impl ImpTcmerr0 {
     #[inline]
     /// Reads IMP_TCMERR0 (*TCM Error Record Register 0*)
     pub fn read() -> ImpTcmerr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_tcmerr1.rs b/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
index 99fea8e3..b04e4514 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
@@ -22,7 +22,7 @@ impl ImpTcmerr1 {
     #[inline]
     /// Reads IMP_TCMERR1 (*TCM Error Record Register 1*)
     pub fn read() -> ImpTcmerr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs b/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
index 38be2914..035d433e 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
@@ -22,6 +22,6 @@ impl ImpTcmsyndr0 {
     #[inline]
     /// Reads IMP_TCMSYNDR0 (*TCM Syndrome Register 0*)
     pub fn read() -> ImpTcmsyndr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs b/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
index e9ba5907..26750cef 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
@@ -22,6 +22,6 @@ impl ImpTcmsyndr1 {
     #[inline]
     /// Reads IMP_TCMSYNDR1 (*TCM Syndrome Register 1*)
     pub fn read() -> ImpTcmsyndr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/imp/imp_testr0.rs b/aarch32-cpu/src/register/imp/imp_testr0.rs
index 1948ad1f..24d779a4 100644
--- a/aarch32-cpu/src/register/imp/imp_testr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_testr0.rs
@@ -22,6 +22,6 @@ impl ImpTestr0 {
     #[inline]
     /// Reads IMP_TESTR0 (*Test Register 0*)
     pub fn read() -> ImpTestr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/iracr.rs b/aarch32-cpu/src/register/iracr.rs
index ae640f09..265bf622 100644
--- a/aarch32-cpu/src/register/iracr.rs
+++ b/aarch32-cpu/src/register/iracr.rs
@@ -44,7 +44,7 @@ impl Iracr {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Iracr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/irbar.rs b/aarch32-cpu/src/register/irbar.rs
index db704204..00838b73 100644
--- a/aarch32-cpu/src/register/irbar.rs
+++ b/aarch32-cpu/src/register/irbar.rs
@@ -25,7 +25,7 @@ impl Irbar {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Irbar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/irsr.rs b/aarch32-cpu/src/register/irsr.rs
index 5e249923..df9ba7e5 100644
--- a/aarch32-cpu/src/register/irsr.rs
+++ b/aarch32-cpu/src/register/irsr.rs
@@ -42,7 +42,7 @@ impl Irsr {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Irsr {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/mair0.rs b/aarch32-cpu/src/register/mair0.rs
index 51ec500b..12d3209e 100644
--- a/aarch32-cpu/src/register/mair0.rs
+++ b/aarch32-cpu/src/register/mair0.rs
@@ -31,7 +31,7 @@ impl Mair0 {
     #[inline]
     /// Reads MAIR0 (*Memory Attribute Indirection Register 0*)
     pub fn read() -> Mair {
-        unsafe { Mair::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Mair::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/mair1.rs b/aarch32-cpu/src/register/mair1.rs
index 95081c73..532bb821 100644
--- a/aarch32-cpu/src/register/mair1.rs
+++ b/aarch32-cpu/src/register/mair1.rs
@@ -23,7 +23,7 @@ impl Mair1 {
     #[inline]
     /// Reads MAIR1 (*Memory Attribute Indirection Register 1*)
     pub fn read() -> Mair {
-        unsafe { Mair::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Mair::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/midr.rs b/aarch32-cpu/src/register/midr.rs
index 055c2746..300ac2ce 100644
--- a/aarch32-cpu/src/register/midr.rs
+++ b/aarch32-cpu/src/register/midr.rs
@@ -38,8 +38,7 @@ impl Midr {
     /// Read MIDR (*Main ID Register*)
     #[inline]
     pub fn read() -> Midr {
-        // Safety: Reading this register has no side-effects and is atomic
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/mod.rs b/aarch32-cpu/src/register/mod.rs
index 94a79de4..1b12d65c 100644
--- a/aarch32-cpu/src/register/mod.rs
+++ b/aarch32-cpu/src/register/mod.rs
@@ -1,4 +1,6 @@
-//! CPU system register access code
+//! Defines various AArch32 system registers
+//!
+//! These are all ready using Co-Processor read/write instructions
 
 pub mod actlr;
 pub mod actlr2;
@@ -204,9 +206,10 @@ pub use vmpidr::Vmpidr;
 pub use vpidr::Vpidr;
 pub use vsctlr::Vsctlr;
 
-#[cfg(any(test, doc, arm_architecture = "v8-r"))]
-pub mod armv8r;
-#[cfg(any(test, doc, arm_architecture = "v8-r"))]
+#[cfg(any(test, arm_architecture = "v8-r"))]
+mod armv8r;
+#[cfg(any(test, arm_architecture = "v8-r"))]
+#[doc(inline)]
 pub use armv8r::*;
 
 #[cfg(any(test, doc, arm_architecture = "v7-a", arm_architecture = "v8-r"))]
@@ -239,10 +242,9 @@ pub trait SysReg {
 pub trait SysRegRead: SysReg {
     /// Read a value from this 32-bit register
     ///
-    /// # Safety
-    ///
-    /// You need to read the Architecture Reference Manual because this read
-    /// may have side-effects.
+    /// Our working assumption is that no Arm system register read has
+    /// side-effects that can cause Undefined Behaviour, so this method
+    /// is safe.
     #[cfg_attr(not(feature = "check-asm"), inline)]
     #[cfg_attr(
         any(
@@ -252,7 +254,7 @@ pub trait SysRegRead: SysReg {
         ),
         instruction_set(arm::a32)
     )]
-    unsafe fn read_raw() -> u32 {
+    fn read_raw() -> u32 {
         let r: u32;
         #[cfg(target_arch = "arm")]
         unsafe {
@@ -323,12 +325,11 @@ pub trait SysReg64 {
 pub trait SysRegRead64: SysReg64 {
     /// Read a value from this 64-bit register
     ///
-    /// # Safety
-    ///
-    /// You need to read the Architecture Reference Manual because this read
-    /// may have side-effects.
+    /// Our working assumption is that no Arm system register read has
+    /// side-effects that can cause Undefined Behaviour, so this method
+    /// is safe.
     #[inline]
-    unsafe fn read_raw() -> u64 {
+    fn read_raw() -> u64 {
         let r_lo: u32;
         let r_hi: u32;
         #[cfg(target_arch = "arm")]
diff --git a/aarch32-cpu/src/register/mpidr.rs b/aarch32-cpu/src/register/mpidr.rs
index 2495b24d..e7fd85f0 100644
--- a/aarch32-cpu/src/register/mpidr.rs
+++ b/aarch32-cpu/src/register/mpidr.rs
@@ -22,6 +22,6 @@ impl Mpidr {
     #[inline]
     /// Reads MPIDR (*Multiprocessor Affinity Register*)
     pub fn read() -> Mpidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/mpuir.rs b/aarch32-cpu/src/register/mpuir.rs
index f28df795..80bada6d 100644
--- a/aarch32-cpu/src/register/mpuir.rs
+++ b/aarch32-cpu/src/register/mpuir.rs
@@ -33,7 +33,7 @@ impl Mpuir {
     #[inline]
     /// Reads MPUIR (*MPU Type Register*)
     pub fn read() -> Mpuir {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/nsacr.rs b/aarch32-cpu/src/register/nsacr.rs
index d9806578..929a00f8 100644
--- a/aarch32-cpu/src/register/nsacr.rs
+++ b/aarch32-cpu/src/register/nsacr.rs
@@ -22,6 +22,6 @@ impl Nsacr {
     #[inline]
     /// Reads NSACR (*Non-Secure Access Control Register*)
     pub fn read() -> Nsacr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/par.rs b/aarch32-cpu/src/register/par.rs
index ac29f584..48b23fe8 100644
--- a/aarch32-cpu/src/register/par.rs
+++ b/aarch32-cpu/src/register/par.rs
@@ -22,7 +22,7 @@ impl Par {
     #[inline]
     /// Reads PAR (*Physical Address Register*)
     pub fn read() -> Par {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmccfiltr.rs b/aarch32-cpu/src/register/pmccfiltr.rs
index 2dcd5ba7..fbd04a0f 100644
--- a/aarch32-cpu/src/register/pmccfiltr.rs
+++ b/aarch32-cpu/src/register/pmccfiltr.rs
@@ -22,7 +22,7 @@ impl Pmccfiltr {
     #[inline]
     /// Reads PMCCFILTR (*Performance Monitors Cycle Count Filter Register*)
     pub fn read() -> Pmccfiltr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmccntr.rs b/aarch32-cpu/src/register/pmccntr.rs
index 63ab0dc9..d653d957 100644
--- a/aarch32-cpu/src/register/pmccntr.rs
+++ b/aarch32-cpu/src/register/pmccntr.rs
@@ -22,7 +22,7 @@ impl Pmccntr {
     #[inline]
     /// Reads PMCCNTR (*Performance Monitors Cycle Count Register*)
     pub fn read() -> Pmccntr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmceid0.rs b/aarch32-cpu/src/register/pmceid0.rs
index dd87cd76..9983f4b4 100644
--- a/aarch32-cpu/src/register/pmceid0.rs
+++ b/aarch32-cpu/src/register/pmceid0.rs
@@ -22,6 +22,6 @@ impl Pmceid0 {
     #[inline]
     /// Reads PMCEID0 (*Performance Monitors Common Event Identification Register 0*)
     pub fn read() -> Pmceid0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/pmceid1.rs b/aarch32-cpu/src/register/pmceid1.rs
index 2d250970..135b3551 100644
--- a/aarch32-cpu/src/register/pmceid1.rs
+++ b/aarch32-cpu/src/register/pmceid1.rs
@@ -22,6 +22,6 @@ impl Pmceid1 {
     #[inline]
     /// Reads PMCEID1 (*Performance Monitors Common Event Identification Register 1*)
     pub fn read() -> Pmceid1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/pmcntenclr.rs b/aarch32-cpu/src/register/pmcntenclr.rs
index 3eceb9dc..4febee74 100644
--- a/aarch32-cpu/src/register/pmcntenclr.rs
+++ b/aarch32-cpu/src/register/pmcntenclr.rs
@@ -22,7 +22,7 @@ impl Pmcntenclr {
     #[inline]
     /// Reads PMCNTENCLR (*Performance Monitors Count Enable Clear Register*)
     pub fn read() -> Pmcntenclr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmcntenset.rs b/aarch32-cpu/src/register/pmcntenset.rs
index dfc07bfb..46904d4d 100644
--- a/aarch32-cpu/src/register/pmcntenset.rs
+++ b/aarch32-cpu/src/register/pmcntenset.rs
@@ -22,7 +22,7 @@ impl Pmcntenset {
     #[inline]
     /// Reads PMCNTENSET (*Performance Monitors Count Enable Set Register*)
     pub fn read() -> Pmcntenset {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmcr.rs b/aarch32-cpu/src/register/pmcr.rs
index df22c6c0..82a1d519 100644
--- a/aarch32-cpu/src/register/pmcr.rs
+++ b/aarch32-cpu/src/register/pmcr.rs
@@ -22,7 +22,7 @@ impl Pmcr {
     #[inline]
     /// Reads PMCR (*Performance Monitors Control Register*)
     pub fn read() -> Pmcr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmevcntr0.rs b/aarch32-cpu/src/register/pmevcntr0.rs
index cbdf038c..8784e306 100644
--- a/aarch32-cpu/src/register/pmevcntr0.rs
+++ b/aarch32-cpu/src/register/pmevcntr0.rs
@@ -22,7 +22,7 @@ impl Pmevcntr0 {
     #[inline]
     /// Reads PMEVCNTR0 (*Performance Monitors Event Count Register 0*)
     pub fn read() -> Pmevcntr0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmevcntr1.rs b/aarch32-cpu/src/register/pmevcntr1.rs
index 4f0b0cb2..33150df8 100644
--- a/aarch32-cpu/src/register/pmevcntr1.rs
+++ b/aarch32-cpu/src/register/pmevcntr1.rs
@@ -22,7 +22,7 @@ impl Pmevcntr1 {
     #[inline]
     /// Reads PMEVCNTR1 (*Performance Monitors Event Count Register 1*)
     pub fn read() -> Pmevcntr1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmevcntr2.rs b/aarch32-cpu/src/register/pmevcntr2.rs
index d2c9bc97..4a6fc972 100644
--- a/aarch32-cpu/src/register/pmevcntr2.rs
+++ b/aarch32-cpu/src/register/pmevcntr2.rs
@@ -22,7 +22,7 @@ impl Pmevcntr2 {
     #[inline]
     /// Reads PMEVCNTR2 (*Performance Monitors Event Count Register 2 *)
     pub fn read() -> Pmevcntr2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmevcntr3.rs b/aarch32-cpu/src/register/pmevcntr3.rs
index 4ce3865e..3991494f 100644
--- a/aarch32-cpu/src/register/pmevcntr3.rs
+++ b/aarch32-cpu/src/register/pmevcntr3.rs
@@ -22,7 +22,7 @@ impl Pmevcntr3 {
     #[inline]
     /// Reads PMEVCNTR3 (*Performance Monitors Event Count Register 3*)
     pub fn read() -> Pmevcntr3 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmevtyper0.rs b/aarch32-cpu/src/register/pmevtyper0.rs
index aad9168e..4ec0c8a3 100644
--- a/aarch32-cpu/src/register/pmevtyper0.rs
+++ b/aarch32-cpu/src/register/pmevtyper0.rs
@@ -22,7 +22,7 @@ impl Pmevtyper0 {
     #[inline]
     /// Reads PMEVTYPER0 (*Performance Monitors Event Type Register 0*)
     pub fn read() -> Pmevtyper0 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmevtyper1.rs b/aarch32-cpu/src/register/pmevtyper1.rs
index 3bf58221..4f3a5b15 100644
--- a/aarch32-cpu/src/register/pmevtyper1.rs
+++ b/aarch32-cpu/src/register/pmevtyper1.rs
@@ -22,7 +22,7 @@ impl Pmevtyper1 {
     #[inline]
     /// Reads PMEVTYPER1 (*Performance Monitors Event Type Register 1*)
     pub fn read() -> Pmevtyper1 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmevtyper2.rs b/aarch32-cpu/src/register/pmevtyper2.rs
index 8207fe31..a619dfa9 100644
--- a/aarch32-cpu/src/register/pmevtyper2.rs
+++ b/aarch32-cpu/src/register/pmevtyper2.rs
@@ -22,7 +22,7 @@ impl Pmevtyper2 {
     #[inline]
     /// Reads PMEVTYPER2 (*Performance Monitors Event Type Register 2*)
     pub fn read() -> Pmevtyper2 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmevtyper3.rs b/aarch32-cpu/src/register/pmevtyper3.rs
index b5d4bc64..747be2e9 100644
--- a/aarch32-cpu/src/register/pmevtyper3.rs
+++ b/aarch32-cpu/src/register/pmevtyper3.rs
@@ -22,7 +22,7 @@ impl Pmevtyper3 {
     #[inline]
     /// Reads PMEVTYPER3 (*Performance Monitors Event Type Register 3*)
     pub fn read() -> Pmevtyper3 {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmintenclr.rs b/aarch32-cpu/src/register/pmintenclr.rs
index f82eac07..91b90d71 100644
--- a/aarch32-cpu/src/register/pmintenclr.rs
+++ b/aarch32-cpu/src/register/pmintenclr.rs
@@ -22,7 +22,7 @@ impl Pmintenclr {
     #[inline]
     /// Reads PMINTENCLR (*Performance Monitors Interrupt Enable Clear Register*)
     pub fn read() -> Pmintenclr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmintenset.rs b/aarch32-cpu/src/register/pmintenset.rs
index fbf35887..cad15f7a 100644
--- a/aarch32-cpu/src/register/pmintenset.rs
+++ b/aarch32-cpu/src/register/pmintenset.rs
@@ -22,7 +22,7 @@ impl Pmintenset {
     #[inline]
     /// Reads PMINTENSET (*Performance Monitors Interrupt Enable Set Register*)
     pub fn read() -> Pmintenset {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmovsr.rs b/aarch32-cpu/src/register/pmovsr.rs
index c0634198..03c557bc 100644
--- a/aarch32-cpu/src/register/pmovsr.rs
+++ b/aarch32-cpu/src/register/pmovsr.rs
@@ -22,7 +22,7 @@ impl Pmovsr {
     #[inline]
     /// Reads PMOVSR (*Performance Monitor Overflow Flag Status Clear Register*)
     pub fn read() -> Pmovsr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmovsset.rs b/aarch32-cpu/src/register/pmovsset.rs
index 4ad574f8..99fc4e2d 100644
--- a/aarch32-cpu/src/register/pmovsset.rs
+++ b/aarch32-cpu/src/register/pmovsset.rs
@@ -22,7 +22,7 @@ impl Pmovsset {
     #[inline]
     /// Reads PMOVSSET (*Performance Monitor Overflow Flag Status Set Register*)
     pub fn read() -> Pmovsset {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmselr.rs b/aarch32-cpu/src/register/pmselr.rs
index 7a7b44d7..39cf337a 100644
--- a/aarch32-cpu/src/register/pmselr.rs
+++ b/aarch32-cpu/src/register/pmselr.rs
@@ -22,7 +22,7 @@ impl Pmselr {
     #[inline]
     /// Reads PMSELR (*Performance Monitors Event Counter Selection Register*)
     pub fn read() -> Pmselr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmuserenr.rs b/aarch32-cpu/src/register/pmuserenr.rs
index 266814c4..25c3111d 100644
--- a/aarch32-cpu/src/register/pmuserenr.rs
+++ b/aarch32-cpu/src/register/pmuserenr.rs
@@ -22,7 +22,7 @@ impl Pmuserenr {
     #[inline]
     /// Reads PMUSERENR (*Performance Monitors User Enable Register*)
     pub fn read() -> Pmuserenr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmxevcntr.rs b/aarch32-cpu/src/register/pmxevcntr.rs
index 9c7f7d44..df65c323 100644
--- a/aarch32-cpu/src/register/pmxevcntr.rs
+++ b/aarch32-cpu/src/register/pmxevcntr.rs
@@ -22,7 +22,7 @@ impl Pmxevcntr {
     #[inline]
     /// Reads PMXEVCNTR (*Performance Monitors Selected Event Count Register*)
     pub fn read() -> Pmxevcntr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/pmxevtyper.rs b/aarch32-cpu/src/register/pmxevtyper.rs
index 4be65a2c..dcee14a7 100644
--- a/aarch32-cpu/src/register/pmxevtyper.rs
+++ b/aarch32-cpu/src/register/pmxevtyper.rs
@@ -22,7 +22,7 @@ impl Pmxevtyper {
     #[inline]
     /// Reads PMXEVTYPER (*Performance Monitors Selected Event Type Register*)
     pub fn read() -> Pmxevtyper {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/revidr.rs b/aarch32-cpu/src/register/revidr.rs
index e86dc7ec..9c777979 100644
--- a/aarch32-cpu/src/register/revidr.rs
+++ b/aarch32-cpu/src/register/revidr.rs
@@ -22,6 +22,6 @@ impl Revidr {
     #[inline]
     /// Reads REVIDR (*Revision ID Register*)
     pub fn read() -> Revidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/rgnr.rs b/aarch32-cpu/src/register/rgnr.rs
index c7f05c3b..622ccae4 100644
--- a/aarch32-cpu/src/register/rgnr.rs
+++ b/aarch32-cpu/src/register/rgnr.rs
@@ -24,7 +24,7 @@ impl Rgnr {
     #[inline]
     /// Reads RGNR (*MPU Region Number Register*)
     pub fn read() -> Rgnr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/rvbar.rs b/aarch32-cpu/src/register/rvbar.rs
index 02f79221..3a028769 100644
--- a/aarch32-cpu/src/register/rvbar.rs
+++ b/aarch32-cpu/src/register/rvbar.rs
@@ -23,6 +23,6 @@ impl Rvbar {
     #[inline]
     /// Reads RVBAR (*Reset Vector Base Address Register*)
     pub fn read() -> Rvbar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/sctlr.rs b/aarch32-cpu/src/register/sctlr.rs
index 486857a1..790fbae0 100644
--- a/aarch32-cpu/src/register/sctlr.rs
+++ b/aarch32-cpu/src/register/sctlr.rs
@@ -72,7 +72,7 @@ impl Sctlr {
     /// Read SCTLR (*System Control Register*)
     #[inline]
     pub fn read() -> Self {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 
     /// Write SCTLR (*System Control Register*)
diff --git a/aarch32-cpu/src/register/tcmtr.rs b/aarch32-cpu/src/register/tcmtr.rs
index 19789ce4..96c9c5cf 100644
--- a/aarch32-cpu/src/register/tcmtr.rs
+++ b/aarch32-cpu/src/register/tcmtr.rs
@@ -22,6 +22,6 @@ impl Tcmtr {
     #[inline]
     /// Reads TCMTR (*TCM Type Register*)
     pub fn read() -> Tcmtr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/tlbiall.rs b/aarch32-cpu/src/register/tlbiall.rs
index e6f664eb..c5298367 100644
--- a/aarch32-cpu/src/register/tlbiall.rs
+++ b/aarch32-cpu/src/register/tlbiall.rs
@@ -17,6 +17,7 @@ impl crate::register::SysRegWrite for TlbIAll {}
 
 impl TlbIAll {
     #[inline]
+    /// Writes 0 to TLBIALL (*TLB Invalidate All Register*) to trigger operation
     pub fn write() {
         unsafe { <Self as crate::register::SysRegWrite>::write_raw(0) }
     }
diff --git a/aarch32-cpu/src/register/tlbtr.rs b/aarch32-cpu/src/register/tlbtr.rs
index 41ce0ae1..59dd7097 100644
--- a/aarch32-cpu/src/register/tlbtr.rs
+++ b/aarch32-cpu/src/register/tlbtr.rs
@@ -22,6 +22,6 @@ impl Tlbtr {
     #[inline]
     /// Reads TLBTR (*TLB Type Register*)
     pub fn read() -> Tlbtr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
diff --git a/aarch32-cpu/src/register/tpidrprw.rs b/aarch32-cpu/src/register/tpidrprw.rs
index c6bcc917..24952a95 100644
--- a/aarch32-cpu/src/register/tpidrprw.rs
+++ b/aarch32-cpu/src/register/tpidrprw.rs
@@ -22,7 +22,7 @@ impl Tpidrprw {
     #[inline]
     /// Reads TPIDRPRW (*EL1 Software Thread ID Register*)
     pub fn read() -> Tpidrprw {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/tpidruro.rs b/aarch32-cpu/src/register/tpidruro.rs
index a17fed5b..05d93f0f 100644
--- a/aarch32-cpu/src/register/tpidruro.rs
+++ b/aarch32-cpu/src/register/tpidruro.rs
@@ -22,7 +22,7 @@ impl Tpidruro {
     #[inline]
     /// Reads TPIDRURO (*EL0 Read-Only Software Thread ID Register*)
     pub fn read() -> Tpidruro {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/tpidrurw.rs b/aarch32-cpu/src/register/tpidrurw.rs
index 3733b2e6..97314c08 100644
--- a/aarch32-cpu/src/register/tpidrurw.rs
+++ b/aarch32-cpu/src/register/tpidrurw.rs
@@ -22,7 +22,7 @@ impl Tpidrurw {
     #[inline]
     /// Reads TPIDRURW (*EL0 Read/Write Software Thread ID Register*)
     pub fn read() -> Tpidrurw {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/ttbr0.rs b/aarch32-cpu/src/register/ttbr0.rs
index ea9c8dd2..0373eb2f 100644
--- a/aarch32-cpu/src/register/ttbr0.rs
+++ b/aarch32-cpu/src/register/ttbr0.rs
@@ -87,11 +87,11 @@ pub enum Region {
     /// Normal memory, Outer Non-cacheable
     NonCacheable = 0b00,
     /// Normal memory, Outer Write-Back Write-Allocate Cacheable
-    WriteBackWriteAllocateCacheable = 0b01,
+    WriteBackWriteAllocCacheable = 0b01,
     /// Normal memory, Outer Write-Through Cacheable
     WriteThroughCacheable = 0b10,
     /// Normal memory, Outer Write-Back no Write-Allocate Cacheable
-    WriteBackNoWriteAllocateCacheable = 0b11,
+    WriteBackNoWriteAllocCacheable = 0b11,
 }
 
 impl SysReg for Ttbr0 {
@@ -110,7 +110,7 @@ impl Ttbr0 {
     #[inline]
     /// Reads TTBR0 (*Translation Table Base Register 0*)
     pub fn read() -> Ttbr0 {
-        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
+        Self::new_with_raw_value(<Self as SysRegRead>::read_raw())
     }
 
     #[inline]
diff --git a/aarch32-cpu/src/register/vmpidr.rs b/aarch32-cpu/src/register/vmpidr.rs
index 3a0fed37..4d77e4cc 100644
--- a/aarch32-cpu/src/register/vmpidr.rs
+++ b/aarch32-cpu/src/register/vmpidr.rs
@@ -22,7 +22,7 @@ impl Vmpidr {
     #[inline]
     /// Reads VMPIDR (*Virtualization Multiprocessor ID Register*)
     pub fn read() -> Vmpidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/vpidr.rs b/aarch32-cpu/src/register/vpidr.rs
index 2e824158..122bd511 100644
--- a/aarch32-cpu/src/register/vpidr.rs
+++ b/aarch32-cpu/src/register/vpidr.rs
@@ -22,7 +22,7 @@ impl Vpidr {
     #[inline]
     /// Reads VPIDR (*Virtualization Processor ID Register*)
     pub fn read() -> Vpidr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/register/vsctlr.rs b/aarch32-cpu/src/register/vsctlr.rs
index dfc92587..d17d45e3 100644
--- a/aarch32-cpu/src/register/vsctlr.rs
+++ b/aarch32-cpu/src/register/vsctlr.rs
@@ -22,7 +22,7 @@ impl Vsctlr {
     #[inline]
     /// Reads VSCTLR (*Virtualization System Control Register*)
     pub fn read() -> Vsctlr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        Self(<Self as SysRegRead>::read_raw())
     }
 }
 
diff --git a/aarch32-cpu/src/stacks.rs b/aarch32-cpu/src/stacks.rs
index 161902f7..20ee7a2a 100644
--- a/aarch32-cpu/src/stacks.rs
+++ b/aarch32-cpu/src/stacks.rs
@@ -33,30 +33,32 @@ pub unsafe fn stack_used_bytes(stack: core::ops::Range<*const u32>) -> (usize, u
 /// of at least `size` words in length.
 unsafe fn stack_unused_bytes_asm(start: *const u32, size: usize) -> usize {
     let result: usize;
-    core::arch::asm!(
-        r#"
-        // skip out if size is zero
-        movs    {result}, #0
-        cmp     {size}, #0
-        beq     3f
-2:      // loop
-        ldr     {scratch}, [{start}]
-        cmp     {scratch}, #0
-        // break out if value is non-zero
-        bne     3f
-        // otherwise increment counter
-        adds    {result}, {result}, #1
-        adds    {start}, {start}, #4
-        // loop if not finished yet
-        cmp     {result}, {size}
-        bne     2b
-        // all finished
-3:
-        "#,
-        size = in(reg) size,
-        start = inout(reg) start => _,
-        result = out(reg) result,
-        scratch = out(reg) _,
-    );
+    unsafe {
+        core::arch::asm!(
+            r#"
+            // skip out if size is zero
+            movs    {result}, #0
+            cmp     {size}, #0
+            beq     3f
+    2:      // loop
+            ldr     {scratch}, [{start}]
+            cmp     {scratch}, #0
+            // break out if value is non-zero
+            bne     3f
+            // otherwise increment counter
+            adds    {result}, {result}, #1
+            adds    {start}, {start}, #4
+            // loop if not finished yet
+            cmp     {result}, {size}
+            bne     2b
+            // all finished
+    3:
+            "#,
+            size = in(reg) size,
+            start = inout(reg) start => _,
+            result = out(reg) result,
+            scratch = out(reg) _,
+        );
+    }
     result
 }
diff --git a/aarch32-rt/src/lib.rs b/aarch32-rt/src/lib.rs
index 04bb2824..46ceb92d 100644
--- a/aarch32-rt/src/lib.rs
+++ b/aarch32-rt/src/lib.rs
@@ -569,7 +569,7 @@ pub mod stacks;
 ///
 /// We end up here if an exception fires and the weak 'PROVIDE' in the link.x
 /// file hasn't been over-ridden.
-#[no_mangle]
+#[unsafe(no_mangle)]
 pub extern "C" fn _default_handler() {
     loop {
         core::hint::spin_loop();
@@ -1151,3 +1151,16 @@ core::arch::global_asm!(
     "#,
     irq_fiq = const aarch32_cpu::register::Cpsr::new_with_raw_value(0).with_i(true).with_f(true).raw_value()
 );
+
+/// LLVM intrinsic for memory barriers
+///
+/// Only required on Armv4T and Armv5TE, because Armv6K onwards support atomics.
+#[unsafe(no_mangle)]
+#[cfg(any(arm_architecture = "v4t", arm_architecture = "v5te"))]
+pub extern "C" fn __sync_synchronize() {
+    // we don't have a barrier instruction - the linux kernel just uses an empty inline asm block
+    // so we do the same.
+    unsafe {
+        core::arch::asm!("");
+    }
+}
diff --git a/examples/mps3-an536-el2/src/bin/generic-timer.rs b/examples/mps3-an536-el2/src/bin/generic-timer.rs
index 102a3220..3a20c547 100644
--- a/examples/mps3-an536-el2/src/bin/generic-timer.rs
+++ b/examples/mps3-an536-el2/src/bin/generic-timer.rs
@@ -44,7 +44,7 @@ fn main() -> ! {
     hyp_timer.countdown_set(hyp_timer.frequency_hz() / 5);
     hyp_timer.enable(true);
     // used in interrupt handler
-    drop(hyp_timer);
+    let _ = hyp_timer;
 
     println!("Enabling interrupts...");
     dump_sctlr();
@@ -111,5 +111,5 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
         hsr.get_iss(),
         frame
     );
-    return frame.r0;
+    frame.r0
 }
diff --git a/examples/mps3-an536-el2/src/bin/hvc-a32.rs b/examples/mps3-an536-el2/src/bin/hvc-a32.rs
index 8d12237b..5bb2aa89 100644
--- a/examples/mps3-an536-el2/src/bin/hvc-a32.rs
+++ b/examples/mps3-an536-el2/src/bin/hvc-a32.rs
@@ -34,7 +34,7 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
     if hsr.iss().value() == 0xABCD {
         do_hvc2();
     }
-    return 0x12345678;
+    0x12345678
 }
 
 #[instruction_set(arm::a32)]
diff --git a/examples/mps3-an536-el2/src/bin/hvc-t32.rs b/examples/mps3-an536-el2/src/bin/hvc-t32.rs
index 98ad5808..9b63655c 100644
--- a/examples/mps3-an536-el2/src/bin/hvc-t32.rs
+++ b/examples/mps3-an536-el2/src/bin/hvc-t32.rs
@@ -34,7 +34,7 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
     if hsr.iss().value() == 0xABCD {
         do_hvc2();
     }
-    return 0x12345678;
+    0x12345678
 }
 
 #[instruction_set(arm::t32)]
diff --git a/examples/mps3-an536-el2/src/bin/svc-a32.rs b/examples/mps3-an536-el2/src/bin/svc-a32.rs
index e131b768..02adc0a3 100644
--- a/examples/mps3-an536-el2/src/bin/svc-a32.rs
+++ b/examples/mps3-an536-el2/src/bin/svc-a32.rs
@@ -34,7 +34,7 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
     if hsr.iss().value() == 0xABCD {
         do_svc2();
     }
-    return 0x12345678;
+    0x12345678
 }
 
 #[instruction_set(arm::a32)]
diff --git a/examples/mps3-an536-el2/src/bin/svc-t32.rs b/examples/mps3-an536-el2/src/bin/svc-t32.rs
index 6957aea0..e542a727 100644
--- a/examples/mps3-an536-el2/src/bin/svc-t32.rs
+++ b/examples/mps3-an536-el2/src/bin/svc-t32.rs
@@ -34,7 +34,7 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
     if hsr.iss().value() == 0x12 {
         do_svc2();
     }
-    return 0x12345678;
+    0x12345678
 }
 
 #[instruction_set(arm::t32)]
diff --git a/examples/mps3-an536/src/bin/mpu_setup.rs b/examples/mps3-an536/src/bin/mpu_setup.rs
index ae84cac8..42d5881e 100644
--- a/examples/mps3-an536/src/bin/mpu_setup.rs
+++ b/examples/mps3-an536/src/bin/mpu_setup.rs
@@ -6,7 +6,7 @@
 #![no_main]
 
 use aarch32_cpu::pmsav8::{
-    Cacheable, El1AccessPerms, El1Mpu, El1Region, El1Shareability, MemAttr, RwAllocPolicy,
+    CachePolicy, El1AccessPerms, El1Mpu, El1Region, El1Shareability, MemAttr, RwAllocPolicy,
 };
 use aarch32_rt::{entry, sections::Section, stacks::Stack};
 use semihosting::println;
@@ -31,13 +31,13 @@ const MAIR_DEVICE: u8 = 2;
 static MEM_ATTRS: [MemAttr; 8] = [
     // Read-only Code RAM
     MemAttr::NormalMemory {
-        outer: Cacheable::WriteThroughNonTransient(RwAllocPolicy::R),
-        inner: Cacheable::WriteThroughNonTransient(RwAllocPolicy::R),
+        outer: CachePolicy::WriteThroughNonTransient(RwAllocPolicy::R),
+        inner: CachePolicy::WriteThroughNonTransient(RwAllocPolicy::R),
     },
     // Read-write RAM
     MemAttr::NormalMemory {
-        outer: Cacheable::WriteBackNonTransient(RwAllocPolicy::W),
-        inner: Cacheable::WriteBackNonTransient(RwAllocPolicy::W),
+        outer: CachePolicy::WriteBackNonTransient(RwAllocPolicy::W),
+        inner: CachePolicy::WriteBackNonTransient(RwAllocPolicy::W),
     },
     // Device Memory
     MemAttr::DeviceMemory,
diff --git a/examples/mps3-an536/src/bin/registers.rs b/examples/mps3-an536/src/bin/registers.rs
index 46cb0b9d..5fdce39b 100644
--- a/examples/mps3-an536/src/bin/registers.rs
+++ b/examples/mps3-an536/src/bin/registers.rs
@@ -36,7 +36,7 @@ fn chip_info() {
 #[cfg(arm_architecture = "v7-r")]
 fn mpu_pmsa_v7() {
     use aarch32_cpu::{
-        pmsav7::{CacheablePolicy, Config, MemAttr, Mpu, Region, RegionSize},
+        pmsav7::{Cacheable, Config, MemAttr, Mpu, Region, RegionSize},
         register::Mpuir,
     };
 
@@ -69,8 +69,8 @@ fn mpu_pmsa_v7() {
             enabled: true,
             no_exec: false,
             mem_attr: MemAttr::Cacheable {
-                inner: CacheablePolicy::WriteThroughNoWriteAllocate,
-                outer: CacheablePolicy::NonCacheable,
+                inner: Cacheable::WriteThroughNoWriteAlloc,
+                outer: Cacheable::NonCacheable,
                 shareable: true,
             },
         }],
@@ -90,10 +90,10 @@ fn mpu_pmsa_v7() {
 fn mpu_pmsa_v8() {
     use aarch32_cpu::{
         pmsav8::{
-            Cacheable, El1AccessPerms, El1Config, El1Mpu, El1Region, El1Shareability, MemAttr,
+            CachePolicy, El1AccessPerms, El1Config, El1Mpu, El1Region, El1Shareability, MemAttr,
             RwAllocPolicy,
         },
-        register::{Mpuir, armv8r::*},
+        register::*,
     };
 
     // How many regions?
@@ -261,8 +261,8 @@ fn mpu_pmsa_v8() {
             },
         ],
         memory_attributes: &[MemAttr::NormalMemory {
-            outer: Cacheable::WriteThroughNonTransient(RwAllocPolicy::RW),
-            inner: Cacheable::WriteThroughNonTransient(RwAllocPolicy::RW),
+            outer: CachePolicy::WriteThroughNonTransient(RwAllocPolicy::RW),
+            inner: CachePolicy::WriteThroughNonTransient(RwAllocPolicy::RW),
         }],
     })
     .unwrap();
diff --git a/examples/versatileab/reference/registers-armv7r-none-eabi.out b/examples/versatileab/reference/registers-armv7r-none-eabi.out
index de0f7f8e..a1d95060 100644
--- a/examples/versatileab/reference/registers-armv7r-none-eabi.out
+++ b/examples/versatileab/reference/registers-armv7r-none-eabi.out
@@ -20,7 +20,7 @@ DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false
 DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
-DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAlloc, shareable: true } }
 DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/reference/registers-armv7r-none-eabihf.out b/examples/versatileab/reference/registers-armv7r-none-eabihf.out
index de0f7f8e..a1d95060 100644
--- a/examples/versatileab/reference/registers-armv7r-none-eabihf.out
+++ b/examples/versatileab/reference/registers-armv7r-none-eabihf.out
@@ -20,7 +20,7 @@ DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false
 DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
-DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAlloc, shareable: true } }
 DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/reference/registers-thumbv7r-none-eabi.out b/examples/versatileab/reference/registers-thumbv7r-none-eabi.out
index de0f7f8e..a1d95060 100644
--- a/examples/versatileab/reference/registers-thumbv7r-none-eabi.out
+++ b/examples/versatileab/reference/registers-thumbv7r-none-eabi.out
@@ -20,7 +20,7 @@ DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false
 DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
-DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAlloc, shareable: true } }
 DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out b/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out
index de0f7f8e..a1d95060 100644
--- a/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out
+++ b/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out
@@ -20,7 +20,7 @@ DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false
 DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
-DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAlloc, shareable: true } }
 DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/src/bin/registers.rs b/examples/versatileab/src/bin/registers.rs
index 7951be3c..e882dbb9 100644
--- a/examples/versatileab/src/bin/registers.rs
+++ b/examples/versatileab/src/bin/registers.rs
@@ -29,7 +29,7 @@ fn chip_info() {
 #[cfg(arm_architecture = "v7-r")]
 fn mpu_pmsa_v7() {
     use aarch32_cpu::{
-        pmsav7::{CacheablePolicy, Config, MemAttr, Mpu, Region, RegionSize},
+        pmsav7::{CachePolicy, Config, MemAttr, Mpu, Region, RegionSize},
         register::Mpuir,
     };
 
@@ -62,8 +62,8 @@ fn mpu_pmsa_v7() {
             enabled: true,
             no_exec: false,
             mem_attr: MemAttr::Cacheable {
-                inner: CacheablePolicy::WriteThroughNoWriteAllocate,
-                outer: CacheablePolicy::NonCacheable,
+                inner: CachePolicy::WriteThroughNoWriteAlloc,
+                outer: CachePolicy::NonCacheable,
                 shareable: true,
             },
         }],
diff --git a/examples/versatileab/src/mmu.rs b/examples/versatileab/src/mmu.rs
index 60da0210..afe918a0 100644
--- a/examples/versatileab/src/mmu.rs
+++ b/examples/versatileab/src/mmu.rs
@@ -18,7 +18,7 @@
 //! all the hardware either on the real board or emulated by QEMU.
 
 use aarch32_cpu::mmu::{
-    AccessPermissions, CacheableMemoryAttribute, L1Section, L1Table, MemoryRegionAttributes,
+    AccessPermissions, CachePolicy, L1Section, L1Table, MemoryRegionAttributes,
     NUM_L1_PAGE_TABLE_ENTRIES, SectionAttributes,
 };
 use arbitrary_int::u4;
@@ -32,8 +32,8 @@ const SDRAM_ATTRS: SectionAttributes = SectionAttributes {
     shareable: true,
     access: AccessPermissions::FullAccess,
     memory_attrs: MemoryRegionAttributes::CacheableMemory {
-        inner: CacheableMemoryAttribute::WriteBackWriteAlloc,
-        outer: CacheableMemoryAttribute::WriteBackWriteAlloc,
+        inner: CachePolicy::WriteBackWriteAlloc,
+        outer: CachePolicy::WriteBackWriteAlloc,
     }
     .as_raw(),
     domain: u4::new(0b0),
@@ -84,7 +84,7 @@ pub fn set_mmu() {
         .with_address(core::ptr::addr_of!(MMU_L1_PAGE_TABLE) as usize)
         .with_irgn(false)
         .with_nos(false)
-        .with_rgn(aarch32_cpu::register::ttbr0::Region::WriteBackWriteAllocateCacheable)
+        .with_rgn(aarch32_cpu::register::ttbr0::Region::WriteBackWriteAllocCacheable)
         .with_s(true)
         .with_c(true);
     unsafe { aarch32_cpu::register::Ttbr0::write(ttbr0) }