diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index d990b86a022..e6fa9f25277 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4553,6 +4553,9 @@
 #define PCI_DID_INTEL_PTL_H_GT2_2			0xb0a0
 #define PCI_DID_INTEL_PTL_H_GT2_3			0xb0b0
 #define PCI_DID_INTEL_PTL_H_GT2_4			0xb08f
+#define PCI_DID_INTEL_PTL_H_GT2_5			0xb081
+#define PCI_DID_INTEL_PTL_H_GT2_6			0xb082
+#define PCI_DID_INTEL_PTL_H_GT2_7			0xb083
 #define PCI_DID_INTEL_WCL_GT2_1				0xfd80
 #define PCI_DID_INTEL_WCL_GT2_2				0xfd81
 #define PCI_DID_INTEL_NVL_GT2_1				0xd741
diff --git a/src/mainboard/system76/ptl/Kconfig b/src/mainboard/system76/ptl/Kconfig
new file mode 100644
index 00000000000..7dc756dc039
--- /dev/null
+++ b/src/mainboard/system76/ptl/Kconfig
@@ -0,0 +1,100 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SYSTEM76_PTL_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_GENERIC
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_LOCKDOWN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_SUPPORT_RESIZABLE_BARS
+	select SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_PANTHERLAKE_U_H
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config BOARD_SYSTEM76_LEMP14
+	select BOARD_SYSTEM76_PTL_COMMON
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_INTEL_USB4_RETIMER
+	select HAVE_SPD_IN_CBFS
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
+config BOARD_SYSTEM76_LEMP14_B
+	select BOARD_SYSTEM76_PTL_COMMON
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_INTEL_USB4_RETIMER
+	select HAVE_SPD_IN_CBFS
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
+if BOARD_SYSTEM76_PTL_COMMON
+
+config MAINBOARD_DIR
+	default "system76/ptl"
+
+config VARIANT_DIR
+	default "lemp14" if BOARD_SYSTEM76_LEMP14 || BOARD_SYSTEM76_LEMP14_B
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	default "lemp14" if BOARD_SYSTEM76_LEMP14
+	default "lemp14-b" if BOARD_SYSTEM76_LEMP14_B
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Lemur Pro" if BOARD_SYSTEM76_LEMP14 || BOARD_SYSTEM76_LEMP14_B
+
+config MAINBOARD_VERSION
+	default "lemp14" if BOARD_SYSTEM76_LEMP14
+	default "lemp14-b" if BOARD_SYSTEM76_LEMP14_B
+
+config CMOS_DEFAULT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
+
+config CONSOLE_POST
+	default y
+
+config D3COLD_SUPPORT
+	default n
+
+config DIMM_SPD_SIZE
+	default 512
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
+	default 36
+
+config POST_DEVICE
+	default n
+
+config TPM_MEASURED_BOOT
+	default y
+
+config UART_FOR_CONSOLE
+	default 0
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif
diff --git a/src/mainboard/system76/ptl/Kconfig.name b/src/mainboard/system76/ptl/Kconfig.name
new file mode 100644
index 00000000000..c598dde5353
--- /dev/null
+++ b/src/mainboard/system76/ptl/Kconfig.name
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_SYSTEM76_LEMP14
+	bool "lemp14"
+
+config BOARD_SYSTEM76_LEMP14_B
+	bool "lemp14-b"
diff --git a/src/mainboard/system76/ptl/Makefile.mk b/src/mainboard/system76/ptl/Makefile.mk
new file mode 100644
index 00000000000..dca14e6c367
--- /dev/null
+++ b/src/mainboard/system76/ptl/Makefile.mk
@@ -0,0 +1,15 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
+
+SPD_SOURCES = Foresee-16GB-FX5P2004G-60 Foresee-32GB-FX5P4008G-60 Micron-16GB-MT62F1G32D2DS-023 Micron-32GB-MT62F2G32D4DS-023
diff --git a/src/mainboard/system76/ptl/acpi/backlight.asl b/src/mainboard/system76/ptl/acpi/backlight.asl
new file mode 100644
index 00000000000..053ce57b5d4
--- /dev/null
+++ b/src/mainboard/system76/ptl/acpi/backlight.asl
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		100, /* default AC */
+		100, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}
diff --git a/src/mainboard/system76/ptl/acpi/mainboard.asl b/src/mainboard/system76/ptl/acpi/mainboard.asl
new file mode 100644
index 00000000000..92fefd20bb9
--- /dev/null
+++ b/src/mainboard/system76/ptl/acpi/mainboard.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI GPE0_ESPI
+#define EC_GPE_SWI GPE0_PME
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
diff --git a/src/mainboard/system76/ptl/acpi/sleep.asl b/src/mainboard/system76/ptl/acpi/sleep.asl
new file mode 100644
index 00000000000..8a2a22c55b6
--- /dev/null
+++ b/src/mainboard/system76/ptl/acpi/sleep.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+External(\TBTS, MethodObj)
+
+Method(MPTS, 1, Serialized) {
+	If (CondRefOf(\TBTS)) {
+		\TBTS()
+	}
+}
diff --git a/src/mainboard/system76/ptl/board_info.txt b/src/mainboard/system76/ptl/board_info.txt
new file mode 100644
index 00000000000..e67d8800620
--- /dev/null
+++ b/src/mainboard/system76/ptl/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: System76
+Category: laptop
+ROM package: WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/ptl/bootblock.c b/src/mainboard/system76/ptl/bootblock.c
new file mode 100644
index 00000000000..8d06adc9d7f
--- /dev/null
+++ b/src/mainboard/system76/ptl/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}
diff --git a/src/mainboard/system76/ptl/cmos.default b/src/mainboard/system76/ptl/cmos.default
new file mode 100644
index 00000000000..0cc5970e49b
--- /dev/null
+++ b/src/mainboard/system76/ptl/cmos.default
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+me_state=Disable
diff --git a/src/mainboard/system76/ptl/cmos.layout b/src/mainboard/system76/ptl/cmos.layout
new file mode 100644
index 00000000000..b3df3808ccb
--- /dev/null
+++ b/src/mainboard/system76/ptl/cmos.layout
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+412	4	e	6	debug_level
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+
+# CMOS_VSTART_ramtop
+800	80	r	0	ramtop
+
+984	16	h	0	check_sum
+
+enumerations
+
+2	0	Enable
+2	1	Disable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+checksums
+
+checksum 408 799 984
diff --git a/src/mainboard/system76/ptl/devicetree.cb b/src/mainboard/system76/ptl/devicetree.cb
new file mode 100644
index 00000000000..7ee39ad59cd
--- /dev/null
+++ b/src/mainboard/system76/ptl/devicetree.cb
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/pantherlake
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "true"
+
+	# Thermal
+	register "tcc_offset" = "8"
+
+	# Enable Energy Reporting
+	register "pch_pm_energy_report_enable" = "true"
+
+	device domain 0 on
+		device ref npu on end
+		device ref iaa off end
+		device ref pmc_shared_sram on end
+		device ref cnvi_wifi on
+			register "cnvi_wifi_core" = "true"
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref soc_espi on
+			register "gen1_dec" = "0x00040069" # EC PM channel
+			register "gen2_dec" = "0x00fc0e01" # AP/EC command
+			register "gen3_dec" = "0x00fc0f01" # AP/EC debug
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref pmc hidden
+			register "pmc_gpe0_dw0" = "GPP_A"
+			register "pmc_gpe0_dw1" = "GPP_D"
+			register "pmc_gpe0_dw2" = "GPP_E"
+		end
+		device ref hda on
+			register "pch_hda_audio_link_hda_enable" = "1"
+			register "pch_hda_sdi_enable[0]" = "true"
+			register "pch_hda_idisp_codec_enable" = "1"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+		end
+		device ref smbus on end
+	end
+end
diff --git a/src/mainboard/system76/ptl/dsdt.asl b/src/mainboard/system76/ptl/dsdt.asl
new file mode 100644
index 00000000000..f6e4cf756bf
--- /dev/null
+++ b/src/mainboard/system76/ptl/dsdt.asl
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS
+#include <soc/gpio.h>
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/pantherlake/acpi/southbridge.asl>
+		#include <soc/intel/pantherlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/ptl/include/mainboard/gpio.h b/src/mainboard/system76/ptl/include/mainboard/gpio.h
new file mode 100644
index 00000000000..c6393beebb6
--- /dev/null
+++ b/src/mainboard/system76/ptl/include/mainboard/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/system76/ptl/ramstage.c b/src/mainboard/system76/ptl/ramstage.c
new file mode 100644
index 00000000000..a3b12bb1f2e
--- /dev/null
+++ b/src/mainboard/system76/ptl/ramstage.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};
diff --git a/src/mainboard/system76/ptl/spd/Foresee-16GB-FX5P2004G-60.spd.hex b/src/mainboard/system76/ptl/spd/Foresee-16GB-FX5P2004G-60.spd.hex
new file mode 100644
index 00000000000..c852010c722
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/Foresee-16GB-FX5P2004G-60.spd.hex
@@ -0,0 +1,33 @@
+# Foresee-16GB-FX5P2004G-60
+23 10 15 0e 86 22 95 08 00 40 00 00 02 01 00 00
+48 00 09 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7f c6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/spd/Foresee-32GB-FX5P4008G-60.spd.hex b/src/mainboard/system76/ptl/spd/Foresee-32GB-FX5P4008G-60.spd.hex
new file mode 100644
index 00000000000..d468db80bd7
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/Foresee-32GB-FX5P4008G-60.spd.hex
@@ -0,0 +1,33 @@
+# Foresee-32GB-FX5P4008G-60
+23 10 15 0e 86 22 b5 08 00 40 00 00 0a 01 00 00
+48 00 09 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7f c6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/spd/Micron-16GB-MT62F1G32D2DS-023.spd.hex b/src/mainboard/system76/ptl/spd/Micron-16GB-MT62F1G32D2DS-023.spd.hex
new file mode 100644
index 00000000000..c566640ec54
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/Micron-16GB-MT62F1G32D2DS-023.spd.hex
@@ -0,0 +1,33 @@
+# Micron-16GB-MT62F1G32D2DS-023
+23 10 13 0e 16 22 95 08 00 40 00 00 02 01 00 00
+48 00 0a ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7f 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/spd/Micron-32GB-MT62F2G32D4DS-023.spd.hex b/src/mainboard/system76/ptl/spd/Micron-32GB-MT62F2G32D4DS-023.spd.hex
new file mode 100644
index 00000000000..f9b37252a16
--- /dev/null
+++ b/src/mainboard/system76/ptl/spd/Micron-32GB-MT62F2G32D4DS-023.spd.hex
@@ -0,0 +1,33 @@
+# Micron-32GB-MT62F2G32D4DS-023
+23 10 15 0e 86 22 b5 08 00 40 00 00 0a 01 00 00
+48 00 08 ff 92 55 05 00 aa 00 90 a8 90 c0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7f c2 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/ptl/variants/lemp14/board.fmd b/src/mainboard/system76/ptl/variants/lemp14/board.fmd
new file mode 100644
index 00000000000..aec4da22f06
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/board.fmd
@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_ME 9176K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 512K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}
diff --git a/src/mainboard/system76/ptl/variants/lemp14/board_info.txt b/src/mainboard/system76/ptl/variants/lemp14/board_info.txt
new file mode 100644
index 00000000000..75ed180caf4
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/board_info.txt
@@ -0,0 +1,2 @@
+Board name: lemp14
+Release year: 2026
diff --git a/src/mainboard/system76/ptl/variants/lemp14/data.vbt b/src/mainboard/system76/ptl/variants/lemp14/data.vbt
new file mode 100644
index 00000000000..d7979238a97
Binary files /dev/null and b/src/mainboard/system76/ptl/variants/lemp14/data.vbt differ
diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio.c b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
new file mode 100644
index 00000000000..3fa6e72d328
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio.c
@@ -0,0 +1,224 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST), // SD_PWR_EN
+	PAD_CFG_GPI(GPP_A09, NONE, PLTRST),
+	PAD_NC(GPP_A10, NONE),
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST), // WLAN_RST#
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BODYSAR#
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_GPO(GPP_A16, 1, DEEP), // PCH_BT_EN
+	PAD_CFG_GPO(GPP_A17, 1, DEEP), // WIFI_RF_EN
+
+	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), // TBT_I2C_SDA
+	PAD_NC(GPP_B02, NONE),
+	PAD_NC(GPP_B03, NONE),
+	PAD_CFG_GPO(GPP_B04, 0, PLTRST), // Flash Descriptor Security Override strap
+	PAD_NC(GPP_B05, NONE),
+	PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_B07, NONE),
+	PAD_NC(GPP_B08, NONE),
+	//PAD_CFG_GPO(GPP_B09, 0, PLTRST), // M2_SSD1_RST#
+	//PAD_CFG_GPO(GPP_B10, 1, PLTRST), // SSD1_PWR_EN
+	PAD_CFG_GPI(GPP_B11, NONE, PLTRST),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), // CPU_HDMI_HPD
+	PAD_CFG_GPI(GPP_B15, NONE, PLTRST), // USB_OC3#
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_CFG_GPO(GPP_B20, 1, PLTRST), // LTE_RST_N
+	PAD_CFG_GPO(GPP_B21, 1, DEEP), // DG_FORCE_PWR
+	PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 0, PLTRST), // strap
+	PAD_NC(GPP_B24, NONE),
+	PAD_NC(GPP_B25, NONE),
+
+	//PAD_CFG_GPI(GPP_C00, UP_20K, PLTRST), // BOARD_ID5
+	//PAD_CFG_GPI(GPP_C01, UP_20K, PLTRST), // BOARD_ID6
+	PAD_CFG_GPO(GPP_C02, 1, PLTRST), // TLS confidentiality strap
+	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPO(GPP_C05, 0, PLTRST), // eSPI disable strap
+	PAD_NC(GPP_C06, NONE),
+	PAD_NC(GPP_C07, NONE),
+	PAD_NC(GPP_C08, NONE),
+	PAD_NC(GPP_C09, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), // CARD_CLKREQ#_N
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), // WLAN_CLKREQ#_N
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), // 5G_PCIE_CLKREQ#_N
+	PAD_NC(GPP_C15, NONE), // Reserved strap
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBTA_LSX0_TXD
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBTA_LSX0_RXD
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), // HDMI_CTRLDATA
+
+	PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON
+	PAD_NC(GPP_D01, NONE),
+	PAD_NC(GPP_D02, NONE),
+	PAD_NC(GPP_D03, NONE),
+	PAD_NC(GPP_D04, NONE),
+	PAD_NC(GPP_D05, NONE),
+	PAD_NC(GPP_D06, NONE),
+	PAD_NC(GPP_D07, NONE),
+	PAD_NC(GPP_D08, NONE),
+	PAD_NC(GPP_D09, NONE),
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / No Reboot strap
+	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_NC(GPP_D14, NONE),
+	PAD_CFG_GPI(GPP_D15, NONE, DEEP), // CNVI_WAKE#
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_D17, NONE),
+	//PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SSD1_CLKREQ#_N
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SD_PCIE_RST_N
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+	PAD_NC(GPP_D24, NONE),
+	PAD_NC(GPP_D25, NONE),
+
+	_PAD_CFG_STRUCT(GPP_E01, 0x42880100, 0x0000), // TPM_PIRQ#
+	PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2), // VRALERT#
+	PAD_NC(GPP_E03, NONE),
+	PAD_NC(GPP_E05, NONE),
+	PAD_CFG_GPO(GPP_E06, 0, PLTRST), // JTAG ODT strap
+	PAD_NC(GPP_E07, NONE),
+	PAD_CFG_GPI(GPP_E08, NONE, DEEP), // WAKE_ON_WWAN_N
+	PAD_CFG_GPI(GPP_E09, NONE, PLTRST), // USB_OC0#
+	PAD_NC(GPP_E10, NONE),
+	//PAD_CFG_GPI(GPP_E11, NONE, PLTRST), // BOARD_ID1
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), // AMP_SMB_CLK
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), // AMP_SMB_DATA
+	//PAD_CFG_GPI(GPP_E14, NONE, PLTRST), // BOARD_ID2
+	//PAD_CFG_GPI(GPP_E15, NONE, PLTRST), // BOARD_ID3
+	PAD_NC(GPP_E16, NONE),
+	//PAD_CFG_GPI(GPP_E17, NONE, PLTRST), // BOARD_ID4
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+	PAD_NC(GPP_E20, NONE),
+	PAD_CFG_NF(GPP_E21, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_NC(GPP_E22, NONE),
+
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT / M.2 CNVi mode strap
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_NC(GPP_F06, NONE), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F07, NONE),
+	PAD_NC(GPP_F08, NONE),
+	PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET
+	PAD_NC(GPP_F10, NONE),
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), // I2C_SDA_TP
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_CFG_GPO(GPP_F16, 1, PLTRST), // CCD_WP#
+	PAD_NC(GPP_F17, NONE),
+	PAD_CFG_GPI_APIC_LOW(GPP_F18, NONE, PLTRST), // TP_ATTN#_N
+	PAD_CFG_GPO(GPP_F19, 1, DEEP), // Reserved strap
+	PAD_NC(GPP_F20, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	PAD_CFG_GPO(GPP_H00, 0, PLTRST), // eSPI Flash Sharing strap (MAFS/SAFS)
+	PAD_CFG_GPO(GPP_H01, 0, PLTRST), // Flash Descriptor Recovery strap
+	PAD_CFG_GPO(GPP_H02, 0, PLTRST), // Reserved strap
+	PAD_CFG_GPO(GPP_H03, 0, DEEP), // PCH_MUTE
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	PAD_NC(GPP_H06, NONE),
+	PAD_NC(GPP_H07, NONE),
+	//PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART_RX
+	//PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART_TX
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL
+
+	PAD_NC(GPP_S00, NONE),
+	PAD_NC(GPP_S01, NONE),
+	PAD_NC(GPP_S02, NONE),
+	PAD_NC(GPP_S03, NONE),
+	PAD_NC(GPP_S04, NONE),
+	PAD_NC(GPP_S05, NONE),
+	PAD_NC(GPP_S06, NONE),
+	PAD_NC(GPP_S07, NONE),
+
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // SOC_WAKE#
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // CPU_PWR_BTN#
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), // SLP_A#
+	PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), // SUS_CLK
+	PAD_NC(GPP_V08, NONE), // SLP_WLAN#
+	PAD_NC(GPP_V09, NONE),
+	PAD_NC(GPP_V10, NONE),
+	PAD_NC(GPP_V11, NONE),
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), // PCH_WAKE#
+	PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), // VCCST_EN
+	PAD_NC(GPP_V17, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static const struct pad_config nvme_pwr_seq2[] = {
+	PAD_CFG_GPO(GPP_B10, 1, PLTRST), // SSD1_PWR_EN
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SSD1_CLKREQ#_N
+};
+
+static void nvme_enable_power(void *unused)
+{
+	gpio_configure_pads(nvme_pwr_seq2, ARRAY_SIZE(nvme_pwr_seq2));
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, nvme_enable_power, NULL);
+
+static const struct pad_config nvme_pwr_seq3[] = {
+	PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_SSD1_RST#
+};
+
+static void nvme_deassert_perst(void *unused)
+{
+	gpio_configure_pads(nvme_pwr_seq3, ARRAY_SIZE(nvme_pwr_seq3));
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, nvme_deassert_perst, NULL);
diff --git a/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c b/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
new file mode 100644
index 00000000000..0029784719f
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/gpio_early.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	// Model detection
+	PAD_CFG_GPI(GPP_E11, NONE, PLTRST), // BOARD_ID1: 0=DRAM_32G, 1=DRAM_16G
+	PAD_CFG_GPI(GPP_E14, NONE, PLTRST), // BOARD_ID2: 0=14", 1=16"
+	PAD_CFG_GPI(GPP_E15, NONE, PLTRST), // BOARD_ID3: 0=FORESEE, 1=MICRON
+	PAD_CFG_GPI(GPP_E17, NONE, PLTRST), // BOARD_ID4: ?
+	PAD_CFG_GPI(GPP_C00, NONE, PLTRST), // BOARD_ID5: 0=SAMSUNG, 1=UNDEFINED
+	PAD_CFG_GPI(GPP_C01, NONE, PLTRST), // BOARD_ID6: ?
+
+	// Debug
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
+
+	// SSD
+	PAD_CFG_GPO(GPP_B09, 0, PLTRST), // M2_SSD1_RST#
+	PAD_CFG_GPO(GPP_B10, 0, PLTRST), // SSD1_PWR_EN
+	PAD_CFG_GPI(GPP_D18, NONE, DEEP), // SSD1_CLKREQ#_N
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c b/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c
new file mode 100644
index 00000000000..2ba7d2befd2
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/hda_verb.c
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+static const u32 realtek_alc245_verbs[] = {
+	AZALIA_SUBVENDOR(0, 0x15582a00),
+	AZALIA_RESET(1),
+
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL | AZALIA_GEOLOCATION_NA,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		3,
+		0
+	)),
+	AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_DESC(
+		AZALIA_NC,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_GEOLOCATION_NA,
+		AZALIA_LINE_OUT,
+		AZALIA_TYPE_UNKNOWN,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		0,
+		0
+	)),
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL | AZALIA_GEOLOCATION_NA,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1,
+		0
+	)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC(
+		AZALIA_NC,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR,
+		AZALIA_MODEM_HANDSET_SIDE,
+		AZALIA_MULTICHANNEL_ANALOG,
+		AZALIA_PINK,
+		0xb,
+		2,
+		0xd
+	)),
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		2,
+		0
+	)),
+
+	//TODO: VERIFY THESE COMMANDS
+	0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
+	0x0205004a, 0x02042010, 0x02050038, 0x02046909,
+	0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
+	0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
+	0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
+	0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
+	0x05450000, 0x05442000, 0x0545001d, 0x05440800,
+	0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
+	0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
+	0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
+	0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
+	0x02050010, 0x02040020, 0x02050010, 0x02040020,
+	0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
+	0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
+	0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
+	0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
+	0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
+	0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
+	0x02050003, 0x02040002, 0x02050069, 0x02040000,
+	0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
+	0x02050010, 0x02040020, 0x02050010, 0x02040020,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+struct azalia_codec mainboard_azalia_codecs[] = {
+	{
+		.name = "Realtek ALC245",
+		.vendor_id = 0x10ec0245,
+		.subsystem_id = 0x15582a00,
+		.address = 0,
+		.verbs = realtek_alc245_verbs,
+		.verb_count = ARRAY_SIZE(realtek_alc245_verbs),
+	}
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb b/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb
new file mode 100644
index 00000000000..8a8536f8a23
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/overridetree.cb
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/pantherlake
+	register "common_soc_config" = "{
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	register "power_limits_config[PTL_CORE_3]" = "{
+		.tdp_pl1_override = 25,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
+	}"
+	register "power_limits_config[PTL_CORE_4]" = "{
+		.tdp_pl1_override = 25,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 152,
+	}"
+
+	device domain 0 on
+		subsystemid 0x1558 0x2a00 inherit
+
+		device ref igpu on
+			# DDIA is eDP, TCP3 is HDMI
+			register "ddi_port_A_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD,
+				[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+
+			chip drivers/gfx/generic
+				register "device_count" = "3"
+				# DDIA: eDP
+				register "device[0].name" = ""LCD0""
+				register "device[0].type" = "panel"
+				# TCP0: TBT
+				register "device[1].name" = ""DD01""
+				register "device[1].use_pld" = "true"
+				register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))"
+				# TCP3: HDMI
+				register "device[2].name" = ""DD02""
+				device generic 0 on end
+			end
+		end
+		device ref tbt_pcie_rp0 on end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-A""
+						register "type" = "UPC_TYPE_USB3_A"
+						device ref tcss_usb3_port2 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port0 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),		/* USB Type-C */
+				[1] = USB2_PORT_MID(OC_SKIP),		/* TBT Type-C */
+				[2] = USB2_PORT_MID(OC_SKIP),		/* USB 3.2 Gen 2 Type-A */
+				[4] = USB2_PORT_MID(OC_SKIP),		/* USB 3.2 Gen 1 Type-A */
+				[5] = USB2_PORT_MID(OC_SKIP),		/* 3G/5G LTE */
+				[6] = USB2_PORT_MID(OC_SKIP),		/* Camera */
+				[7] = USB2_PORT_MID(OC_SKIP),		/* Bluetooth */
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB 3.2 Gen 1 Type-A */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* 3G/5G LTE */
+			}"
+		end
+
+		device ref i2c4 on
+			# Smart Amplifier
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci"
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+		end
+		device ref i2c5 on
+			# Touchpad
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+
+		device ref pcie_rp1 on
+			# SSD
+			register "pcie_rp[PCIE_RP(1)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "srcclk_pin" = "6"
+				device generic 0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+		end
+		device ref pcie_rp7 on
+			# CARD
+			register "pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)"
+				register "enable_delay_ms" = "100"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
+				register "reset_delay_ms" = "20"
+				register "srcclk_pin" = "3"
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			# WLAN
+			register "pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "srcclk_pin" = "4"
+				device generic 0 on end
+			end
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+		end
+	end
+end
diff --git a/src/mainboard/system76/ptl/variants/lemp14/romstage.c b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
new file mode 100644
index 00000000000..8f805327a40
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/romstage.c
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+// Verified from lemp14 schematic mappings
+static const struct mb_cfg board_cfg = {
+	.type = MEM_TYPE_LP5X,
+
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  13,  14,  12,  15, 11,  10,  8,  9, },
+			.dq1 = {  7,  5,  4,  6,  0,  3,  1,  2 },
+		},
+		.ddr1 = {
+			.dq0 = {  1,  3,  0,  2,  7,  4,  6,  5, },
+			.dq1 = {  12,  13,  14,  15,  11,  10,  9,  8 },
+		},
+		.ddr2 = {
+			.dq0 = {  0,  2,  1,  3,  6,  4,  7,  5 },
+			.dq1 = {  14,  13,  15,  12,  8,  11,  10,  9, },
+		},
+		.ddr3 = {
+			.dq0 = {  6,  5,  7,  4,  2,  3,  1,  0, },
+			.dq1 = {  10,  8,  11,  9,  12,  15,  13,  14 },
+		},
+		.ddr4 = {
+			.dq0 = {  2,  1,  3,  0,  4,  7,  5,  6 },
+			.dq1 = {  15,  14,  12,  13,  9,  11,  10,  8, },
+		},
+		.ddr5 = {
+			.dq0 = {  6,  5,  7,  4,  3,  1,  0,  2, },
+			.dq1 = {  10,  9,  11,  8,  13,  14,  12,  15 },
+		},
+		.ddr6 = {
+			.dq0 = {  9,  10,  11,  8,  14,  12,  13, 15, },
+			.dq1 = {  0,  1,  2,  3,  5,  7,  4,  6 },
+		},
+		.ddr7 = {
+			.dq0 = {  0,  1,  2,  3,  7,  5,  6,  4, },
+			.dq1 = {  14,  13,  15,  12,  10,  8,  11,  9 },
+		},
+	},
+
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.user_bd = BOARD_TYPE_ULT_ULX,
+
+	.lp5x_config = {
+		.ccc_config = 0xFF,
+	},
+};
+
+static size_t get_spd_index(void)
+{
+	// 0: Foresee 16 GiB
+	// 1: Foresee 32 GiB
+	// 2: Micron 16 GiB
+	// 3: Micron 32 GiB
+	size_t index = 0;
+	if (gpio_get(GPP_E15)) {
+		// If BOARD_ID3 is high, the system uses Micron memory
+		index += 2;
+	}
+	if (!gpio_get(GPP_E11)) {
+		// If BOARD_ID1 is low, the system has 32 GB of RAM
+		index += 1;
+	}
+	return index;
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_MEMORY_DOWN,
+		.cbfs_index = get_spd_index(),
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
diff --git a/src/mainboard/system76/ptl/variants/lemp14/tas5825m.c b/src/mainboard/system76/ptl/variants/lemp14/tas5825m.c
new file mode 100644
index 00000000000..171d9c1ed20
--- /dev/null
+++ b/src/mainboard/system76/ptl/variants/lemp14/tas5825m.c
@@ -0,0 +1,1049 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <delay.h>
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+int tas5825m_setup(struct device *dev, int id)
+{
+	int res;
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x01, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	mdelay(5);
+
+	res = tas5825m_write_at(dev, 0x03, 0x12);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x48, 0x0C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x7F, 0x64);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00,
+			0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27,
+			0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0,
+			0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3,
+			0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5,
+			0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7,
+			0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA,
+			0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05,
+			0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8,
+			0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9,
+			0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20,
+			0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A,
+			0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48,
+			0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32,
+			0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00,
+			0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0,
+			0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48,
+			0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02,
+			0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F,
+			0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF,
+			0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1,
+			0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00,
+			0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F,
+			0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11,
+			0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01,
+			0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67,
+			0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02,
+			0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9,
+			0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0,
+			0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA,
+			0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC,
+			0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05,
+			0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08,
+			0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D,
+			0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82,
+			0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC,
+			0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00,
+			0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0,
+			0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1,
+			0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3,
+			0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1,
+			0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5,
+			0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x08);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9,
+			0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10,
+			0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB,
+			0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20,
+			0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30,
+			0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0,
+			0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4,
+			0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6,
+			0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x09);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0,
+			0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA,
+			0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC,
+			0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81,
+			0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00,
+			0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30,
+			0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76,
+			0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01,
+			0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46,
+			0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82,
+			0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0,
+			0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66,
+			0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00,
+			0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B,
+			0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46,
+			0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26,
+			0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81,
+			0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28,
+			0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24,
+			0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4,
+			0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10,
+			0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00,
+			0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80,
+			0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D,
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01,
+			0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02,
+			0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F,
+			0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A,
+			0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30,
+			0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE,
+			0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E,
+			0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8,
+			0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF,
+			0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1,
+			0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A,
+			0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F,
+			0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80,
+			0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD,
+			0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF,
+			0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50,
+			0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00,
+			0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00,
+			0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E,
+			0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33,
+			0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83,
+			0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00,
+			0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09,
+			0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00,
+			0x8F, 0x00, 0x00, 0x01, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x78);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x18);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1C);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1D);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x1E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1,
+			0xF8, 0x59, 0x7F, 0x63, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9,
+			0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48,
+			0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76,
+			0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x10);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x40, 0x00);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x11, 0xFF, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x51, 0x05);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x19, 0xDF);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x46, 0x11);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x02, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x53, 0x01);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x54, 0x17);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x7F, 0x8C);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x71, 0x94, 0x9A, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0A);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0B);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x28, 0x7A, 0x27,
+			0x00, 0x28, 0x7A, 0x27, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xEE, 0xC9, 0x55,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x7F, 0xF9, 0x2C, 0x60, 0x07, 0x77, 0x1A, 0x4F,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x07);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x80, 0x00, 0x00, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	{
+		const uint8_t values[] = {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0xAA);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_set_page(dev, 0x01);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x02);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x03);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x07, 0xC5, 0xCA, 0x98,
+			0xF0, 0x74, 0x6A, 0xD0, 0x07, 0xC5, 0xCA, 0x98,
+			0x0F, 0x8A, 0x9A, 0x1D, 0xF8, 0x73, 0x6F, 0xBD,
+			0x07, 0xCC, 0x4D, 0x23, 0xF0, 0x8F, 0xEC, 0x92,
+			0x07, 0xA8, 0xA9, 0xB4, 0x0F, 0x70, 0x13, 0x6E,
+			0xF8, 0x8B, 0x09, 0x29, 0x08, 0x2F, 0x93, 0x82,
+			0xF0, 0x34, 0x1D, 0x7A, 0x07, 0xA1, 0x4F, 0x7F,
+			0x0F, 0xCD, 0x63, 0x79, 0xF8, 0x30, 0x9D, 0xF2,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x04);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x05);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x07, 0xC5, 0xCA, 0x98, 0xF0, 0x74, 0x6A, 0xD0,
+			0x07, 0xC5, 0xCA, 0x98, 0x0F, 0x8A, 0x9A, 0x1D,
+			0xF8, 0x73, 0x6F, 0xBD, 0x07, 0xCC, 0x4D, 0x23,
+			0xF0, 0x8F, 0xEC, 0x92, 0x07, 0xA8, 0xA9, 0xB4,
+			0x0F, 0x70, 0x13, 0x6E, 0xF8, 0x8B, 0x09, 0x29,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x06);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x2F, 0x93, 0x82, 0xF0, 0x34, 0x1D, 0x7A,
+			0x07, 0xA1, 0x4F, 0x7F, 0x0F, 0xCD, 0x63, 0x79,
+			0xF8, 0x30, 0x9D, 0xF2, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0E);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x00, 0x91, 0xDC, 0xC5, 0xFF, 0x04, 0xF3, 0x02,
+			0x00, 0x6E, 0x34, 0x0A, 0x0F, 0xD6, 0x6C, 0x7A,
+			0xF8, 0x24, 0x8F, 0xB5, 0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_page(dev, 0x0F);
+	if (res < 0)
+		return res;
+
+	{
+		const uint8_t values[] = {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81,
+			0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81,
+			0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1,
+			0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F,
+			0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64,
+			0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7,
+			0x00
+		};
+		res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values));
+		if (res < 0)
+			return res;
+	}
+
+	res = tas5825m_set_book(dev, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x30, 0x00);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x60, 0x02);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x62, 0x09);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x4C, 0x30);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x03, 0x03);
+	if (res < 0)
+		return res;
+
+	res = tas5825m_write_at(dev, 0x78, 0x80);
+	if (res < 0)
+		return res;
+
+	return 0;
+}
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 14893869a0a..6cf5ad9f313 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -373,6 +373,9 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_H_GT2_2,
 	PCI_DID_INTEL_PTL_H_GT2_3,
 	PCI_DID_INTEL_PTL_H_GT2_4,
+	PCI_DID_INTEL_PTL_H_GT2_5,
+	PCI_DID_INTEL_PTL_H_GT2_6,
+	PCI_DID_INTEL_PTL_H_GT2_7,
 	PCI_DID_INTEL_LNL_M_GT2,
 	PCI_DID_INTEL_RPL_U_GT1,
 	PCI_DID_INTEL_RPL_U_GT2,
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index 54238654a62..85c5005db31 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -227,6 +227,51 @@ const char *const *soc_smi_sts_array(size_t *a);
  */
 const char *const *soc_std_gpe_sts_array(size_t *a);
 
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)
+/*
+ * This function returns array of string which represents
+ * names for the STD GPE1 status register bits.
+ * Size of the array is returned as an output parameter.
+ */
+const char *const *soc_std_gpe1_sts_array(int idx, size_t *a);
+
+/*
+ * This function disables the corresponding STD GPE1 EN register bits
+ * based on standard GPE0 EN bits masks.
+ */
+void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask);
+
+/*
+ * This function enables the corresponding STD GPE1 EN register bits
+ * based on standard GPE0 EN bits masks.
+ */
+void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask);
+
+#else
+
+static inline const char *const *soc_std_gpe1_sts_array(int idx, size_t *a)
+{
+	return NULL;
+}
+
+static inline void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask)
+{
+	/* nop */
+}
+
+static inline void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask)
+{
+	/* nop */
+}
+
+#endif
+
+/* This function disables GPE1 bits based on its block mask */
+void pmc_disable_gpe1(int gpe, uint32_t mask);
+
+/* This function enables GPE1 bits based on its block mask */
+void pmc_enable_gpe1(int gpe, uint32_t mask);
+
 /*
  * This function gets the gpe0 dwX values from devicetree
  * for pmc_gpe_init which will use those to set the GPE_CFG
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index dc36d30bdbf..7bdad130177 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -289,39 +289,68 @@ uint32_t pmc_clear_tco_status(void)
 }
 
 /* GPE */
-static void pmc_enable_gpe(int gpe, uint32_t mask)
+static void pmc_enable_gpe0(int gpe, uint32_t mask)
 {
 	uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe));
 	gpe0_en |= mask;
 	outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe));
 }
 
-static void pmc_disable_gpe(int gpe, uint32_t mask)
+void pmc_enable_gpe1(int gpe, uint32_t mask)
+{
+	uint32_t gpe1_en = inl(ACPI_BASE_ADDRESS + GPE1_EN(gpe));
+	gpe1_en |= mask;
+	outl(gpe1_en, ACPI_BASE_ADDRESS + GPE1_EN(gpe));
+}
+
+static void pmc_disable_gpe0(int gpe, uint32_t mask)
 {
 	uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe));
 	gpe0_en &= ~mask;
 	outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe));
 }
 
+void pmc_disable_gpe1(int gpe, uint32_t mask)
+{
+	uint32_t gpe1_en = inl(ACPI_BASE_ADDRESS + GPE1_EN(gpe));
+	gpe1_en &= ~mask;
+	outl(gpe1_en, ACPI_BASE_ADDRESS + GPE1_EN(gpe));
+}
+
 void pmc_enable_std_gpe(uint32_t mask)
 {
-	pmc_enable_gpe(GPE_STD, mask);
+	pmc_enable_gpe0(GPE_STD, mask);
+
+	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1))
+		return;
+
+	soc_pmc_enable_std_gpe1(mask);
 }
 
 void pmc_disable_std_gpe(uint32_t mask)
 {
-	pmc_disable_gpe(GPE_STD, mask);
+	pmc_disable_gpe0(GPE_STD, mask);
+
+	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1))
+		return;
+
+	soc_pmc_disable_std_gpe1(mask);
 }
 
 void pmc_disable_all_gpe(void)
 {
 	int i;
 	for (i = 0; i < GPE0_REG_MAX; i++)
-		pmc_disable_gpe(i, ~0);
+		pmc_disable_gpe0(i, ~0);
+
+	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1))
+		return;
+	for (i = 0; i < GPE1_REG_MAX; i++)
+		pmc_disable_gpe1(i, ~0);
 }
 
 /* Clear the gpio gpe0 status bits in ACPI registers */
-static void pmc_clear_gpi_gpe_status(void)
+static void pmc_clear_gpi_gpe0_status(void)
 {
 	int i;
 
@@ -334,14 +363,25 @@ static void pmc_clear_gpi_gpe_status(void)
 	}
 }
 
-static uint32_t reset_std_gpe_status(void)
+static uint32_t reset_std_gpe0_status(void)
 {
 	uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
 	outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
 	return gpe_sts;
 }
 
-static uint32_t print_std_gpe_sts(uint32_t gpe_sts)
+/* Clear the gpio GPE1 status bits in ACPI registers */
+static void reset_std_gpe1_status(uint32_t *gpe_sts)
+{
+	if (gpe_sts == NULL)
+		return;
+	for (int i = 0; i < GPE1_REG_MAX; i++) {
+		gpe_sts[i] = inl(ACPI_BASE_ADDRESS + GPE1_STS(i));
+		outl(gpe_sts[i], ACPI_BASE_ADDRESS + GPE1_STS(i));
+	}
+}
+
+static uint32_t print_std_gpe0_sts(uint32_t gpe_sts)
 {
 	size_t array_size;
 	const char *const *sts_arr;
@@ -358,15 +398,35 @@ static uint32_t print_std_gpe_sts(uint32_t gpe_sts)
 	return gpe_sts;
 }
 
+static void print_std_gpe1_sts(uint32_t *gpe_sts)
+{
+	size_t array_size;
+	const char *const *sts_arr;
+	if (gpe_sts == NULL)
+		return;
+	for (int i = 0; i < GPE1_REG_MAX; i++) {
+		sts_arr = soc_std_gpe1_sts_array(i, &array_size);
+		printk(BIOS_DEBUG, "GPE1 STD STS[%d]: ", i);
+		print_num_status_bits(array_size, gpe_sts[i], sts_arr);
+	}
+	printk(BIOS_DEBUG, "\n");
+}
+
 static void pmc_clear_std_gpe_status(void)
 {
-	print_std_gpe_sts(reset_std_gpe_status());
+	print_std_gpe0_sts(reset_std_gpe0_status());
+	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1))
+		return;
+	uint32_t gpe1_sts[GPE1_REG_MAX];
+
+	reset_std_gpe1_status(gpe1_sts);
+	print_std_gpe1_sts(gpe1_sts);
 }
 
 void pmc_clear_all_gpe_status(void)
 {
 	pmc_clear_std_gpe_status();
-	pmc_clear_gpi_gpe_status();
+	pmc_clear_gpi_gpe0_status();
 }
 
 __weak
@@ -506,7 +566,14 @@ void pmc_fill_pm_reg_info(struct chipset_power_state *ps)
 		printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
 		       i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
 	}
-
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)
+	for (i = 0; i < GPE1_REG_MAX; i++) {
+		ps->gpe1_sts[i] = inl(ACPI_BASE_ADDRESS + GPE1_STS(i));
+		ps->gpe1_en[i] = inl(ACPI_BASE_ADDRESS + GPE1_EN(i));
+		printk(BIOS_DEBUG, "gpe1_sts[%d]: %08x gpe1_en[%d]: %08x\n",
+			i, ps->gpe1_sts[i], i, ps->gpe1_en[i]);
+	}
+#endif
 	soc_fill_power_state(ps);
 }
 
diff --git a/src/soc/intel/common/feature/pmutil/pmutil.c b/src/soc/intel/common/feature/pmutil/pmutil.c
index 5d7db19f746..64e2ecb09d5 100644
--- a/src/soc/intel/common/feature/pmutil/pmutil.c
+++ b/src/soc/intel/common/feature/pmutil/pmutil.c
@@ -111,6 +111,118 @@ const char *const *soc_std_gpe_sts_array(size_t *a)
 	return gpe_sts_bits;
 }
 
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)
+const char *const *soc_std_gpe1_sts_array(int idx, size_t *a)
+{
+	static const char *const gpe1_sts_bits[GPE1_REG_MAX][32] = {
+		/* 0x10  GPE1_31_0   General Purpose Event 1 Status [31:0] */
+		[0] = {                           /* GPE# dec   hex   GPE1 bit position */
+			[18] = "CNVI_BT_PME_B0",      /*   146      0x92       [18]         */
+			[17] = "TC_IOM_PME_B0",       /*   145      0x91       [17]         */
+			[16] = "TC_TBT1_PME_B0",      /*   144      0x90       [16]         */
+			[15] = "TC_TBT0_PME_B0",      /*   143      0x8F       [15]         */
+			[14] = "LPSS_PME_B0",         /*   142      0x8E       [14]         */
+			[13] = "CSE_PME_B0",          /*   141      0x8D       [13]         */
+			[12] = "XDCI_PME_B0",         /*   140      0x8C       [12]         */
+			[10] = "ACE_PME_B0",          /*   138      0x8A       [10]         */
+			[9] = "XHCI_PME_B0",          /*   137      0x89       [9]          */
+			[8] = "SATA_PME_B0",          /*   136      0x88       [8]          */
+			[7] = "CSME_PME_B0",          /*   135      0x87       [7]          */
+			[6] = "GBE_PME_B0",           /*   134      0x86       [6]          */
+			[5] = "CNVI_PME_B0",          /*   133      0x85       [5]          */
+			[4] = "OSSE_PME_B0",          /*   132      0x84       [4]          */
+			[1] = "TBTLSX_PME_B0",        /*   129      0x81       [1]          */
+		},
+		/* 0x14  GPE1_63_32 General Purpose Event 1 Status [63:32] */
+		[1] = {                            /* GPE# dec  hex   GPE1 bit position */
+			[31] = "PG5_PMA0_HOT_PLUG_3",  /*  191      0xBF       [63]         */
+			[30] = "PG5_PMA0_HOT_PLUG_2",  /*  190      0xBE       [62]         */
+			[29] = "PG5_PMA0_HOT_PLUG_1",  /*  189      0xBD       [61]         */
+			[28] = "PG5_PMA0_HOT_PLUG_0",  /*  188      0xBC       [60]         */
+			[27] = "PG5_PMA1_HOT_PLUG_3",  /*  187      0xBB       [59]         */
+			[26] = "PG5_PMA1_HOT_PLUG_2",  /*  186      0xBA       [58]         */
+			[25] = "PG5_PMA1_HOT_PLUG_1",  /*  185      0xB9       [57]         */
+			[24] = "PG5_PMA1_HOT_PLUG_0",  /*  184      0xB8       [56]         */
+			[13] = "TC_TBT1_HOT_PLUG",     /*  173      0xAD       [45]         */
+			[12] = "TC_TBT0_HOT_PLUG",     /*  172      0xAC       [44]         */
+			[11] = "TC_PCIE3_HOT_PLUG",    /*  171      0xAB       [43]         */
+			[10] = "TC_PCIE2_HOT_PLUG",    /*  170      0xAA       [42]         */
+			[9]  = "TC_PCIE1_HOT_PLUG",    /*  169      0xA9       [41]         */
+			[8]  = "TC_PCIE0_HOT_PLUG",    /*  168      0xA8       [40]         */
+			[7]  = "IOE_HOT_PLUG",         /*  167      0xA7       [39]         */
+			[1]  = "SPB_HOT_PLUG",         /*  161      0xA1       [33]         */
+			[0]  = "SPA_HOT_PLUG",         /*  160      0xA0       [32]         */
+		},
+		/* 0x18  GPE1_95_64 General Purpose Event 1 Status [63:32] */
+		[2] = {                            /* GPE# dec  hex   GPE1 bit position */
+			[31] = "PG5_PMA0_PCI_EXP_3",   /*  223      0xDF       [95]         */
+			[30] = "PG5_PMA0_PCI_EXP_2",   /*  222      0xDE       [94]         */
+			[29] = "PG5_PMA0_PCI_EXP_1",   /*  221      0xDD       [93]         */
+			[28] = "PG5_PMA0_PCI_EXP_0",   /*  220      0xDC       [92]         */
+			[27] = "PG5_PMA1_PCI_EXP_3",   /*  219      0xDB       [91]         */
+			[26] = "PG5_PMA1_PCI_EXP_2",   /*  218      0xDA       [90]         */
+			[25] = "PG5_PMA1_PCI_EXP_1",   /*  217      0xD9       [89]         */
+			[24] = "PG5_PMA1_PCI_EXP_0",   /*  216      0xD8       [88]         */
+			[13] = "TC_TBT1_PCI_EXP",      /*  205      0xCD       [77]         */
+			[12] = "TC_TBT0_PCI_EXP",      /*  204      0xCC       [76]         */
+			[11] = "TC_PCIE3_PCI_EXP",     /*  203      0xCb       [75]         */
+			[10] = "TC_PCIE2_PCI_EXP",     /*  202      0xCA       [74]         */
+			[9]  = "TC_PCIE1_PCI_EXP",     /*  201      0xC9       [73]         */
+			[8]  = "TC_PCIE0_PCI_EXP",     /*  200      0xC8       [72]         */
+			[7]  = "IOE_PCI_EXP",          /*  199      0xC7       [71]         */
+			[1]  = "SPB_PCI_EXP",          /*  193      0xC1       [65]         */
+			[0]  = "SPA_PCI_EXP",          /*  192      0xC0       [64]         */
+		}
+	};
+	*a = ARRAY_SIZE(gpe1_sts_bits[idx]);
+	return gpe1_sts_bits[idx];
+}
+
+/* disable the corresponding GPE1 bits based on STD GPE0 bits */
+void soc_pmc_disable_std_gpe1(uint32_t std_gpe0_mask)
+{
+	if (std_gpe0_mask & PME_B0_EN)
+		pmc_disable_gpe1(GPE1_EN(0), GPE1_PME_B0_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & TC_PME_B0_EN)
+		pmc_disable_gpe1(GPE1_EN(0), GPE1_TC_PME_B0_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & HOT_PLUG_STS)
+		pmc_disable_gpe1(GPE1_EN(1), GPE1_HOT_PLUG_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & TC_HOT_PLUG_EN)
+		pmc_disable_gpe1(GPE1_EN(1), GPE1_TC_HOT_PLUG_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & PCI_EXP_EN)
+		pmc_disable_gpe1(GPE1_EN(2), GPE1_PCI_EXP_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & TC_PCI_EXP_EN)
+		pmc_disable_gpe1(GPE1_EN(2), GPE1_TC_PCI_EXP_EVENT_EN_BITS);
+}
+
+/* enable the corresponding GPE1 bits based on STD GPE0 bits */
+void soc_pmc_enable_std_gpe1(uint32_t std_gpe0_mask)
+{
+	if (std_gpe0_mask & PME_B0_EN)
+		pmc_enable_gpe1(GPE1_EN(0), GPE1_PME_B0_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & TC_PME_B0_EN)
+		pmc_enable_gpe1(GPE1_EN(0), GPE1_TC_PME_B0_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & HOT_PLUG_STS)
+		pmc_enable_gpe1(GPE1_EN(1), GPE1_HOT_PLUG_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & TC_HOT_PLUG_EN)
+		pmc_enable_gpe1(GPE1_EN(1), GPE1_TC_HOT_PLUG_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & PCI_EXP_EN)
+		pmc_enable_gpe1(GPE1_EN(2), GPE1_PCI_EXP_EVENT_EN_BITS);
+
+	if (std_gpe0_mask & TC_PCI_EXP_EN)
+		pmc_enable_gpe1(GPE1_EN(2), GPE1_TC_PCI_EXP_EVENT_EN_BITS);
+}
+#endif
+
 void pmc_set_disb(void)
 {
 	/* Set the DISB after DRAM init */
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig
index 00616f14a57..1bfe0b59faa 100644
--- a/src/soc/intel/pantherlake/Kconfig
+++ b/src/soc/intel/pantherlake/Kconfig
@@ -112,6 +112,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1
 	select SOC_INTEL_CRASHLOG
 	select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU
 	select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS
diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c
index bf769d952ab..678b6f91208 100644
--- a/src/soc/intel/pantherlake/acpi.c
+++ b/src/soc/intel/pantherlake/acpi.c
@@ -107,7 +107,6 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
 static int cstate_set_non_s0ix[] = {
 	C_STATE_C1,
 	C_STATE_C6_LONG_LAT,
-	C_STATE_C7S_LONG_LAT
 };
 
 /* TODO: Update as per PTL spec */
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 70d644ff527..d5320c58f5c 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -157,6 +157,9 @@ static struct {
 	{ PCI_DID_INTEL_PTL_H_GT2_2, "Pantherlake-H GT2" },
 	{ PCI_DID_INTEL_PTL_H_GT2_3, "Pantherlake-H GT2" },
 	{ PCI_DID_INTEL_PTL_H_GT2_4, "Pantherlake-H GT2" },
+	{ PCI_DID_INTEL_PTL_H_GT2_5, "Pantherlake-H GT2" },
+	{ PCI_DID_INTEL_PTL_H_GT2_6, "Pantherlake-H GT2" },
+	{ PCI_DID_INTEL_PTL_H_GT2_7, "Pantherlake-H GT2" },
 	{ PCI_DID_INTEL_WCL_GT2_1, "Wildcatlake GT2" },
 	{ PCI_DID_INTEL_WCL_GT2_2, "Wildcatlake GT2" },
 };
diff --git a/src/soc/intel/pantherlake/include/soc/gpe.h b/src/soc/intel/pantherlake/include/soc/gpe.h
index eb9a8bff85b..974326fdcc0 100644
--- a/src/soc/intel/pantherlake/include/soc/gpe.h
+++ b/src/soc/intel/pantherlake/include/soc/gpe.h
@@ -4,5 +4,217 @@
 #define _SOC_PANTHERLAKE_GPE_H_
 
 #include <intelpch/gpe.h>
+#include <soc/pm.h>
+
+/* additional GPE_STD bits in PTL GPE0 blocks */
+/* 0x6C GPE0_STS_127_96; 0x7C GPE0_EN_127_96 */
+#define GPE0_FIA_DFLEX      96  /* _L60 */
+
+#define GPE0_THERM          100 /* _L64 */
+#define GPE0_TC_PME_B0      101 /* _L65 */
+
+#define GPE0_ISH            104 /* _L68 */
+
+#define GPE0_ME_SCI         108 /* _L6C */
+
+#define GPE0_USB_CON_DSX    113 /* _L71 */
+
+#define GPE0_TCSS_SX_WAKE   115 /* _L73 */
+#define GPE0_TC_PCI_EXP     118 /* _L76 */
+#define GPE0_TC_HOT_PLUG    119 /* _L77 */
+#define GPE0_OSSE_SCI       120 /* _L78 */
+
+#undef GPE_MAX
+#define GPE_MAX  GPE0_OSSE_SCI
+
+
+/*
+ * NOTE: GPE1 number starts right after GPE0 events and GPE0 number starts from
+ * 0. that is:
+ * 0 + (number of GPE0 blocks x block size (i.e. 4 bytes) x 8 (byte = 8 bits))
+ * In most of the cases, this value is 0x80 (128 dec)
+ */
+#define GPE1_START_NUM (GPE0_REG_MAX * 4 * 8)
+#define GPE1_NUM(blk, bit) (GPE1_START_NUM + (blk) * 32 + (bit))
+#define GPE1_0_NUM(b) GPE1_NUM(GPE1_31_0, b)
+#define GPE1_1_NUM(b) GPE1_NUM(GPE1_63_32, b)
+#define GPE1_2_NUM(b) GPE1_NUM(GPE1_95_64, b)
+
+/* 0x10 GPE1_STS_31_0; 0x1C GPE1_EN_31_0 register bit fields */
+#define GPE1_31_0_CNVI_BT_PME_B0       18
+#define GPE1_31_0_TC_IOM_PME_B0        17
+#define GPE1_31_0_TC_TBT1_PME_B0       16
+#define GPE1_31_0_TC_TBT0_PME_B0       15
+#define GPE1_31_0_LPSS_PME_B0          14
+#define GPE1_31_0_CSE_PME_B0           13
+#define GPE1_31_0_XDCI_PME_B0          12
+#define GPE1_31_0_ACE_PME_B0           10
+#define GPE1_31_0_XHCI_PME_B0          9
+#define GPE1_31_0_SATA_PME_B0          8
+#define GPE1_31_0_CSME_PME_B0          7
+#define GPE1_31_0_GBE_PME_B0           6
+#define GPE1_31_0_CNVI_PME_B0          5
+#define GPE1_31_0_OSSE_PME_B0          4
+#define GPE1_31_0_TBTLSX_PME_B0        1
+
+/* 0x14 GPE1_STS_63_32; 0x20 GPE1_EN_63_32 register bit fields */
+#define GPE1_63_32_PG5_PMA0_HOT_PLUG_3 31
+#define GPE1_63_32_PG5_PMA0_HOT_PLUG_2 30
+#define GPE1_63_32_PG5_PMA0_HOT_PLUG_1 29
+#define GPE1_63_32_PG5_PMA0_HOT_PLUG_0 28
+#define GPE1_63_32_PG5_PMA1_HOT_PLUG_3 27
+#define GPE1_63_32_PG5_PMA1_HOT_PLUG_2 26
+#define GPE1_63_32_PG5_PMA1_HOT_PLUG_1 25
+#define GPE1_63_32_PG5_PMA1_HOT_PLUG_0 24
+#define GPE1_63_32_TC_TBT1_HOT_PLUG    13
+#define GPE1_63_32_TC_TBT0_HOT_PLUG    12
+#define GPE1_63_32_TC_PCIE3_HOT_PLUG   11
+#define GPE1_63_32_TC_PCIE2_HOT_PLUG   10
+#define GPE1_63_32_TC_PCIE1_HOT_PLUG   9
+#define GPE1_63_32_TC_PCIE0_HOT_PLUG   8
+#define GPE1_63_32_IOE_HOT_PLUG        7
+#define GPE1_63_32_SPB_HOT_PLUG        1
+#define GPE1_63_32_SPA_HOT_PLUG        0
+
+/* 0x18 GPE1_STS_95_64; 0x24 GPE1_EN_95_64 register bit fields */
+#define GPE1_95_64_PG5_PMA0_PCI_EXP_3  31
+#define GPE1_95_64_PG5_PMA0_PCI_EXP_2  30
+#define GPE1_95_64_PG5_PMA0_PCI_EXP_1  29
+#define GPE1_95_64_PG5_PMA0_PCI_EXP_0  28
+#define GPE1_95_64_PG5_PMA1_PCI_EXP_3  27
+#define GPE1_95_64_PG5_PMA1_PCI_EXP_2  26
+#define GPE1_95_64_PG5_PMA1_PCI_EXP_1  25
+#define GPE1_95_64_PG5_PMA1_PCI_EXP_0  24
+#define GPE1_95_64_TC_TBT1_PCI_EXP     13
+#define GPE1_95_64_TC_TBT0_PCI_EXP     12
+#define GPE1_95_64_TC_PCIE3_PCI_EXP    11
+#define GPE1_95_64_TC_PCIE2_PCI_EXP    10
+#define GPE1_95_64_TC_PCIE1_PCI_EXP    9
+#define GPE1_95_64_TC_PCIE0_PCI_EXP    8
+#define GPE1_95_64_IOE_PCI_EXP         7
+#define GPE1_95_64_SPB_PCI_EXP         1
+#define GPE1_95_64_SPA_PCI_EXP         0
+
+/* GPE1 PME_B0 event numbers */
+#define GPE1_CNVI_BT_PME_B0      GPE1_0_NUM(GPE1_31_0_CNVI_BT_PME_B0)        /* 146: _L92 */
+#define GPE1_TC_IOM_PME_B0       GPE1_0_NUM(GPE1_31_0_TC_IOM_PME_B0)         /* 145: _L91 */
+#define GPE1_TC_TBT1_PME_B0      GPE1_0_NUM(GPE1_31_0_TC_TBT1_PME_B0)        /* 144: _L90 */
+#define GPE1_TC_TBT0_PME_B0      GPE1_0_NUM(GPE1_31_0_TC_TBT0_PME_B0)        /* 143: _L8F */
+#define GPE1_LPSS_PME_B0         GPE1_0_NUM(GPE1_31_0_LPSS_PME_B0)           /* 142: _L8E */
+#define GPE1_CSE_PME_B0          GPE1_0_NUM(GPE1_31_0_CSE_PME_B0)            /* 141: _L8D */
+#define GPE1_XDCI_PME_B0         GPE1_0_NUM(GPE1_31_0_XDCI_PME_B0)           /* 140: _L8C */
+#define GPE1_ACE_PME_B0          GPE1_0_NUM(GPE1_31_0_ACE_PME_B0)            /* 138: _L8A */
+#define GPE1_XHCI_PME_B0         GPE1_0_NUM(GPE1_31_0_XHCI_PME_B0)           /* 137: _L89 */
+#define GPE1_SATA_PME_B0         GPE1_0_NUM(GPE1_31_0_SATA_PME_B0)           /* 136: _L88 */
+#define GPE1_CSME_PME_B0         GPE1_0_NUM(GPE1_31_0_CSME_PME_B0)           /* 135: _L87 */
+#define GPE1_GBE_PME_B0          GPE1_0_NUM(GPE1_31_0_GBE_PME_B0)            /* 134: _L86 */
+#define GPE1_CNVI_PME_B0         GPE1_0_NUM(GPE1_31_0_CNVI_PME_B0)           /* 133: _L85 */
+#define GPE1_OSSE_PME_B0         GPE1_0_NUM(GPE1_31_0_OSSE_PME_B0)           /* 132: _L84 */
+#define GPE1_TBTLSX_PME_B0       GPE1_0_NUM(GPE1_31_0_TBTLSX_PME_B0)         /* 129: _L81 */
+
+/* GPE1 HOT_PUG event numbers */
+#define GPE1_PG5_PMA0_HOT_PLUG_3 GPE1_1_NUM(GPE1_63_32_PG5_PMA0_HOT_PLUG_3) /* 191: _LBF */
+#define GPE1_PG5_PMA0_HOT_PLUG_2 GPE1_1_NUM(GPE1_63_32_PG5_PMA0_HOT_PLUG_2) /* 190: _LBE */
+#define GPE1_PG5_PMA0_HOT_PLUG_1 GPE1_1_NUM(GPE1_63_32_PG5_PMA0_HOT_PLUG_1) /* 189: _LBD */
+#define GPE1_PG5_PMA0_HOT_PLUG_0 GPE1_1_NUM(GPE1_63_32_PG5_PMA0_HOT_PLUG_0) /* 188: _LBC */
+#define GPE1_PG5_PMA1_HOT_PLUG_3 GPE1_1_NUM(GPE1_63_32_PG5_PMA1_HOT_PLUG_3) /* 187: _LBB */
+#define GPE1_PG5_PMA1_HOT_PLUG_2 GPE1_1_NUM(GPE1_63_32_PG5_PMA1_HOT_PLUG_2) /* 186: _LBA */
+#define GPE1_PG5_PMA1_HOT_PLUG_1 GPE1_1_NUM(GPE1_63_32_PG5_PMA1_HOT_PLUG_1) /* 185: _LB9 */
+#define GPE1_PG5_PMA1_HOT_PLUG_0 GPE1_1_NUM(GPE1_63_32_PG5_PMA1_HOT_PLUG_0) /* 184: _LB8 */
+#define GPE1_TC_TBT1_HOT_PLUG    GPE1_1_NUM(GPE1_63_32_TC_TBT1_HOT_PLUG)    /* 173: _LAD */
+#define GPE1_TC_TBT0_HOT_PLUG    GPE1_1_NUM(GPE1_63_32_TC_TBT0_HOT_PLUG)    /* 172: _LAC */
+#define GPE1_TC_PCIE3_HOT_PLUG   GPE1_1_NUM(GPE1_63_32_TC_PCIE3_HOT_PLUG)   /* 171: _LAB */
+#define GPE1_TC_PCIE2_HOT_PLUG   GPE1_1_NUM(GPE1_63_32_TC_PCIE2_HOT_PLUG)   /* 170: _LAA */
+#define GPE1_TC_PCIE1_HOT_PLUG   GPE1_1_NUM(GPE1_63_32_TC_PCIE1_HOT_PLUG)   /* 169: _LA9 */
+#define GPE1_TC_PCIE0_HOT_PLUG   GPE1_1_NUM(GPE1_63_32_TC_PCIE0_HOT_PLUG)   /* 168: _LA8 */
+#define GPE1_IOE_HOT_PLUG        GPE1_1_NUM(GPE1_63_32_IOE_HOT_PLUG)        /* 167: _LA7 */
+#define GPE1_SPB_HOT_PLUG        GPE1_1_NUM(GPE1_63_32_SPB_HOT_PLUG)        /* 161: _LA1 */
+#define GPE1_SPA_HOT_PLUG        GPE1_1_NUM(GPE1_63_32_SPA_HOT_PLUG)        /* 160: _LA0 */
+
+/* GPE1 PCI_EXP event numbers */
+#define GPE1_PG5_PMA0_PCI_EXP_3  GPE1_2_NUM(GPE1_95_64_PG5_PMA0_PCI_EXP_3)  /* 223: _LDF */
+#define GPE1_PG5_PMA0_PCI_EXP_2  GPE1_2_NUM(GPE1_95_64_PG5_PMA0_PCI_EXP_2)  /* 222: _LDE */
+#define GPE1_PG5_PMA0_PCI_EXP_1  GPE1_2_NUM(GPE1_95_64_PG5_PMA0_PCI_EXP_1)  /* 221: _LDD */
+#define GPE1_PG5_PMA0_PCI_EXP_0  GPE1_2_NUM(GPE1_95_64_PG5_PMA0_PCI_EXP_0)  /* 220: _LDC */
+#define GPE1_PG5_PMA1_PCI_EXP_3  GPE1_2_NUM(GPE1_95_64_PG5_PMA1_PCI_EXP_3)  /* 219: _LDB */
+#define GPE1_PG5_PMA1_PCI_EXP_2  GPE1_2_NUM(GPE1_95_64_PG5_PMA1_PCI_EXP_2)  /* 218: _LDA */
+#define GPE1_PG5_PMA1_PCI_EXP_1  GPE1_2_NUM(GPE1_95_64_PG5_PMA1_PCI_EXP_1)  /* 217: _LD9 */
+#define GPE1_PG5_PMA1_PCI_EXP_0  GPE1_2_NUM(GPE1_95_64_PG5_PMA1_PCI_EXP_0)  /* 216: _LD8 */
+#define GPE1_TC_TBT1_PCI_EXP     GPE1_2_NUM(GPE1_95_64_TC_TBT1_PCI_EXP)     /* 205: _LCD */
+#define GPE1_TC_TBT0_PCI_EXP     GPE1_2_NUM(GPE1_95_64_TC_TBT0_PCI_EXP)     /* 204: _LCC */
+#define GPE1_TC_PCIE3_PCI_EXP    GPE1_2_NUM(GPE1_95_64_TC_PCIE3_PCI_EXP)    /* 203: _LCB */
+#define GPE1_TC_PCIE2_PCI_EXP    GPE1_2_NUM(GPE1_95_64_TC_PCIE2_PCI_EXP)    /* 202: _LCA */
+#define GPE1_TC_PCIE1_PCI_EXP    GPE1_2_NUM(GPE1_95_64_TC_PCIE1_PCI_EXP)    /* 201: _LC9 */
+#define GPE1_TC_PCIE0_PCI_EXP    GPE1_2_NUM(GPE1_95_64_TC_PCIE0_PCI_EXP)    /* 200: _LC8 */
+#define GPE1_IOE_PCI_EXP         GPE1_2_NUM(GPE1_95_64_IOE_PCI_EXP)         /* 199: _LC7 */
+#define GPE1_SPB_PCI_EXP         GPE1_2_NUM(GPE1_95_64_SPB_PCI_EXP)         /* 193: _LC1 */
+#define GPE1_SPA_PCI_EXP         GPE1_2_NUM(GPE1_95_64_SPA_PCI_EXP)         /* 192: _LC0 */
+
+/* All PME B0 events except TCSS in GPE1 block 0 */
+#define GPE1_PME_B0_EVENT_EN_BITS ( \
+	CNVI_BT_PME_B0_EN | \
+	LPSS_PME_B0_EN    | \
+	CSE_PME_B0_EN     | \
+	XDCI_PME_B0_EN    | \
+	ACE_PME_B0_EN     | \
+	XHCI_PME_B0_EN    | \
+	SATA_PME_B0_EN    | \
+	CSME_PME_B0_EN    | \
+	GBE_PME_B0_EN     | \
+	CNVI_PME_B0_EN    | \
+	OSSE_PME_B0_EN)
+
+/* All TCSS PME B0 events in GPE1 block 0 */
+#define GPE1_TC_PME_B0_EVENT_EN_BITS ( \
+	TC_IOM_PME_B0_EN | \
+	TC_TBT1_PME_B0_EN| \
+	TC_TBT0_PME_B0_EN| \
+	TBTLSX_PME_B0_EN)
+
+/* All hot plug events except TCSS in GPE1 block 1 */
+#define GPE1_HOT_PLUG_EVENT_EN_BITS ( \
+	PG5_PMA0_HOT_PLUG_EN_3 | \
+	PG5_PMA0_HOT_PLUG_EN_2 | \
+	PG5_PMA0_HOT_PLUG_EN_1 | \
+	PG5_PMA0_HOT_PLUG_EN_0 | \
+	PG5_PMA1_HOT_PLUG_EN_3 | \
+	PG5_PMA1_HOT_PLUG_EN_2 | \
+	PG5_PMA1_HOT_PLUG_EN_1 | \
+	PG5_PMA1_HOT_PLUG_EN_0 | \
+	IOE_HOT_PLUG_EN |        \
+	SPB_HOT_PLUG_EN |        \
+	SPA_HOT_PLUG_EN)
+
+/* All GPE1 TCSS hot plug events in GPE1 block 1 */
+#define GPE1_TC_HOT_PLUG_EVENT_EN_BITS ( \
+	TC_TBT1_HOT_PLUG_EN  | \
+	TC_TBT0_HOT_PLUG_EN  | \
+	TC_PCIE3_HOT_PLUG_EN | \
+	TC_PCIE2_HOT_PLUG_EN | \
+	TC_PCIE1_HOT_PLUG_EN | \
+	TC_PCIE0_HOT_PLUG_EN)
+
+/* All PCIe events except TCSS in GPE1 block 2 */
+#define GPE1_PCI_EXP_EVENT_EN_BITS ( \
+	PG5_PMA0_PCI_EXP_EN_3 | \
+	PG5_PMA0_PCI_EXP_EN_2 | \
+	PG5_PMA0_PCI_EXP_EN_1 | \
+	PG5_PMA0_PCI_EXP_EN_0 | \
+	PG5_PMA1_PCI_EXP_EN_3 | \
+	PG5_PMA1_PCI_EXP_EN_2 | \
+	PG5_PMA1_PCI_EXP_EN_1 | \
+	PG5_PMA1_PCI_EXP_EN_0 | \
+	IOE_PCI_EXP_EN |        \
+	SPB_PCI_EXP_EN |        \
+	SPA_PCI_EXP_EN)
+
+/* All GPE1 TCSS PCIe events in GPE1 block 2 */
+#define GPE1_TC_PCI_EXP_EVENT_EN_BITS ( \
+	TC_TBT1_PCI_EXP_EN  | \
+	TC_TBT0_PCI_EXP_EN  | \
+	TC_PCIE3_PCI_EXP_EN | \
+	TC_PCIE2_PCI_EXP_EN | \
+	TC_PCIE1_PCI_EXP_EN | \
+	TC_PCIE0_PCI_EXP_EN)
 
 #endif /* _SOC_PANTHERLAKE_GPE_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/pm.h b/src/soc/intel/pantherlake/include/soc/pm.h
index b8a86fc83a2..a52afe4e801 100644
--- a/src/soc/intel/pantherlake/include/soc/pm.h
+++ b/src/soc/intel/pantherlake/include/soc/pm.h
@@ -3,82 +3,88 @@
 #ifndef _SOC_PANTHERLAKE_PM_H_
 #define _SOC_PANTHERLAKE_PM_H_
 
-#define  PM1_STS		0x00
-#define   WAK_STS		BIT(15)
-#define   PCIEXPWAK_STS		BIT(14)
-#define   PRBTNOR_STS		BIT(11)
-#define   RTC_STS		BIT(10)
-#define   PWRBTN_STS		BIT(8)
-#define   GBL_STS		BIT(5)
-#define   BM_STS		BIT(4)
-#define   TMROF_STS		BIT(0)
-#define  PM1_EN			0x02
-#define   PCIEXPWAK_DIS		BIT(14)
-#define   RTC_EN		BIT(10)
-#define   PWRBTN_EN		BIT(8)
-#define   GBL_EN		BIT(5)
-#define   TMROF_EN		BIT(0)
-#define  PM1_CNT		0x04
-#define   GBL_RLS		BIT(2)
-#define   BM_RLD		BIT(1)
-#define   SCI_EN		BIT(0)
-#define  PM1_TMR		0x08
-#define  SMI_EN			0x30
-#define   XHCI_SMI_EN		BIT(31)
-#define   ME_SMI_EN		BIT(30)
-#define   ESPI_SMI_EN		BIT(28)
-#define   GPIO_UNLOCK_SMI_EN	BIT(27)
-#define   INTEL_USB2_EN		BIT(18)
-#define   LEGACY_USB2_EN	BIT(17)
-#define   PERIODIC_EN		BIT(14)
-#define   TCO_SMI_EN		BIT(13)
-#define   MCSMI_EN		BIT(11)
-#define   BIOS_RLS		BIT(7)
-#define   SWSMI_TMR_EN		BIT(6)
-#define   APMC_EN		BIT(5)
-#define   SLP_SMI_EN		BIT(4)
-#define   LEGACY_USB_EN		BIT(3)
-#define   BIOS_EN		BIT(2)
-#define   EOS			BIT(1)
-#define   GBL_SMI_EN		BIT(0)
-#define  SMI_STS			0x34
-#define   SMI_STS_BITS			32
-#define   XHCI_SMI_STS_BIT		31
-#define   ME_SMI_STS_BIT		30
-#define   ESPI_SMI_STS_BIT		28
-#define   GPIO_UNLOCK_SMI_STS_BIT	27
-#define   SPI_SMI_STS_BIT		26
-#define   SCC_SMI_STS_BIT		25
-#define   MONITOR_STS_BIT		21
-#define   PCI_EXP_SMI_STS_BIT		20
-#define   SMBUS_SMI_STS_BIT		16
-#define   SERIRQ_SMI_STS_BIT		15
-#define   PERIODIC_STS_BIT		14
-#define   TCO_STS_BIT			13
-#define   DEVMON_STS_BIT		12
-#define   MCSMI_STS_BIT			11
-#define   GPIO_STS_BIT			10
-#define   GPE0_STS_BIT			9
-#define   PM1_STS_BIT			8
-#define   SWSMI_TMR_STS_BIT		6
-#define   APM_STS_BIT			5
-#define   SMI_ON_SLP_EN_STS_BIT		4
-#define   LEGACY_USB_STS_BIT		3
-#define   BIOS_STS_BIT			2
-#define  GPE_CNTL		0x42
-#define   SWGPE_CTRL		BIT(1)
-#define  DEVACT_STS		0x44
-#define  PM2_CNT		0x50
-
-#define  GPE0_REG_MAX		4
-#define  GPE0_REG_SIZE		32
-#define  GPE0_STS(x)		(0x60 + ((x) * 4))
-#define   GPE_31_0		0	/* 0x60/0x70 = GPE[31:0] */
-#define   GPE_63_32		1	/* 0x64/0x74 = GPE[63:32] */
-#define   GPE_95_64		2	/* 0x68/0x78 = GPE[95:64] */
-#define   GPE_STD		3	/* 0x6c/0x7c = Standard GPE */
-#define   GPE_STS_RSVD		GPE_STD
-#define	  WADT_STS		BIT(18)
+#define PM1_STS			0x00
+#define  WAK_STS		BIT(15)
+#define  PCIEXPWAK_STS		BIT(14)
+#define  PRBTNOR_STS		BIT(11)
+#define  RTC_STS		BIT(10)
+#define  PWRBTN_STS		BIT(8)
+#define  GBL_STS		BIT(5)
+#define  BM_STS			BIT(4)
+#define  TMROF_STS		BIT(0)
+#define PM1_EN			0x02
+#define  PCIEXPWAK_DIS		BIT(14)
+#define  RTC_EN			BIT(10)
+#define  PWRBTN_EN		BIT(8)
+#define  GBL_EN			BIT(5)
+#define  TMROF_EN		BIT(0)
+#define PM1_CNT			0x04
+#define  GBL_RLS		BIT(2)
+#define  BM_RLD			BIT(1)
+#define  SCI_EN			BIT(0)
+#define PM1_TMR			0x08
+#define SMI_EN			0x30
+#define  XHCI_SMI_EN		BIT(31)
+#define  ME_SMI_EN		BIT(30)
+#define  ESPI_SMI_EN		BIT(28)
+#define  GPIO_UNLOCK_SMI_EN	BIT(27)
+#define  INTEL_USB2_EN		BIT(18)
+#define  LEGACY_USB2_EN		BIT(17)
+#define  PERIODIC_EN		BIT(14)
+#define  TCO_SMI_EN		BIT(13)
+#define  MCSMI_EN		BIT(11)
+#define  BIOS_RLS		BIT(7)
+#define  SWSMI_TMR_EN		BIT(6)
+#define  APMC_EN		BIT(5)
+#define  SLP_SMI_EN		BIT(4)
+#define  LEGACY_USB_EN		BIT(3)
+#define  BIOS_EN		BIT(2)
+#define  EOS			BIT(1)
+#define  GBL_SMI_EN		BIT(0)
+#define SMI_STS			0x34
+#define  SMI_STS_BITS			32
+#define  XHCI_SMI_STS_BIT		31
+#define  ME_SMI_STS_BIT			30
+#define  ESPI_SMI_STS_BIT		28
+#define  GPIO_UNLOCK_SMI_STS_BIT	27
+#define  SPI_SMI_STS_BIT		26
+#define  SCC_SMI_STS_BIT		25
+#define  MONITOR_STS_BIT		21
+#define  PCI_EXP_SMI_STS_BIT		20
+#define  SMBUS_SMI_STS_BIT		16
+#define  SERIRQ_SMI_STS_BIT		15
+#define  PERIODIC_STS_BIT		14
+#define  TCO_STS_BIT			13
+#define  DEVMON_STS_BIT			12
+#define  MCSMI_STS_BIT			11
+#define  GPIO_STS_BIT			10
+#define  GPE0_STS_BIT			9
+#define  PM1_STS_BIT			8
+#define  SWSMI_TMR_STS_BIT		6
+#define  APM_STS_BIT			5
+#define  SMI_ON_SLP_EN_STS_BIT		4
+#define  LEGACY_USB_STS_BIT		3
+#define  BIOS_STS_BIT			2
+#define GPE_CNTL		0x42
+#define  SWGPE_CTRL		BIT(1)
+#define DEVACT_STS		0x44
+#define PM2_CNT			0x50
+
+#define GPE0_REG_MAX		4
+#define GPE0_REG_SIZE		32
+#define GPE0_STS(x)		(0x60 + ((x) * 4))
+#define  GPE_31_0		0	/* 0x60/0x70 = GPE0[31:0] */
+#define  GPE_63_32		1	/* 0x64/0x74 = GPE0[63:32] */
+#define  GPE_95_64		2	/* 0x68/0x78 = GPE0[95:64] */
+#define  GPE_STD		3	/* 0x6c/0x7c = Standard GPE */
+#define GPE_STS_RSVD		GPE_STD
+#define   OSSE_SCI_STS		BIT(24)
+#define   TC_HOT_PLUG_STS	BIT(23)
+#define   TC_PCI_EXP_STS	BIT(22)
+#define   TCSS_SX_WAKE_STS	BIT(19)
+#define   WADT_STS		BIT(18)
+#define   USB_CON_DSX_STS	BIT(17)
+#define   LANWAKE_STS		BIT(16)
 #define   GPIO_T2_STS		BIT(15)
 #define   ESPI_STS		BIT(14)
 #define   PME_B0_STS		BIT(13)
@@ -86,23 +92,161 @@
 #define   PME_STS		BIT(11)
 #define   BATLOW_STS		BIT(10)
 #define   PCI_EXP_STS		BIT(9)
+#define   ISH_STS		BIT(8)
 #define   SMB_WAK_STS		BIT(7)
 #define   TCOSCI_STS		BIT(6)
+#define   TC_PME_B0_STS		BIT(5)
+#define   THERM_STS		BIT(4)
 #define   SWGPE_STS		BIT(2)
 #define   HOT_PLUG_STS		BIT(1)
-#define  GPE0_EN(x)		(0x70 + ((x) * 4))
+#define   FIA_DFLEX_STS		BIT(0)
+
+#define GPE0_EN(x)		(0x70 + ((x) * 4))
+#define   OSSE_SCI_EN		BIT(24)
+#define   TC_HOT_PLUG_EN	BIT(23)
+#define   TC_PCI_EXP_EN		BIT(22)
+#define   TCSS_SX_WAKE_EN	BIT(19)
 #define   WADT_EN		BIT(18)
+#define   USB_CON_DSX_EN	BIT(17)
+#define   LANWAKE_EN		BIT(16)
 #define   GPIO_T2_EN		BIT(15)
 #define   ESPI_EN		BIT(14)
-#define   PME_B0_EN_BIT		13
-#define   PME_B0_EN		BIT(PME_B0_EN_BIT)
+#define   PME_B0_EN		BIT(13)
 #define   ME_SCI_EN		BIT(12)
 #define   PME_EN		BIT(11)
 #define   BATLOW_EN		BIT(10)
 #define   PCI_EXP_EN		BIT(9)
+#define   ISH_EN		BIT(8)
+/*
+  SMB_WAK_ENi:  bit 7 is reserved
+  NOTE: For Intel PCH, the SMBus slave will always be enabled as a wake event.
+*/
 #define   TCOSCI_EN		BIT(6)
+#define   TC_PME_B0_EN		BIT(5)
+#define   THERM_EN		BIT(4)
 #define   SWGPE_EN		BIT(2)
 #define   HOT_PLUG_EN		BIT(1)
+#define   FIA_DFLEX_EN		BIT(0)
+
+#define EN_BLOCK		3
+
+/*
+ * SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is set for PTL SoC, hence the
+ * following three GPE1_* macros are required.
+ */
+#define GPE1_REG_MAX	3
+#define GPE1_EN(x)	(0x1c + ((x) * 4))
+#define GPE1_STS(x)	(0x10 + ((x) * 4))
+
+#define GPE1_REG_SIZE	32
+#define  GPE1_31_0		0	/* 0x10/0x1c = GPE1[31:0]  */
+#define  GPE1_63_32		1	/* 0x14/0x20 = GPE1[63:32] */
+#define  GPE1_95_64		2	/* 0x18/0x2c = GPE1[95:64] */
+
+/* 0x10		GPE1_STS_31_0	General Purpose Event 1 Status [31:0] */
+#define CNVI_BT_PME_B0_STS	BIT(18)
+#define TC_IOM_PME_B0_STS	BIT(17)
+#define TC_TBT1_PME_B0_STS	BIT(16)
+#define TC_TBT0_PME_B0_STS	BIT(15)
+#define LPSS_PME_B0_STS		BIT(14)
+#define CSE_PME_B0_STS		BIT(13)
+#define XDCI_PME_B0_STS		BIT(12)
+#define ACE_PME_B0_STS		BIT(10)
+#define XHCI_PME_B0_STS		BIT(9)
+#define SATA_PME_B0_STS		BIT(8)
+#define CSME_PME_B0_STS		BIT(7)
+#define GBE_PME_B0_STS		BIT(6)
+#define CNVI_PME_B0_STS		BIT(5)
+#define OSSE_PME_B0_STS		BIT(4)
+#define TBTLSX_PME_B0_STS	BIT(1)
+/* 0x14		GPE1_STS_63_32	General Purpose Event 1 Status [63:32] */
+#define PG5_PMA0_HOT_PLUG_STS_3	BIT(31)
+#define PG5_PMA0_HOT_PLUG_STS_2	BIT(30)
+#define PG5_PMA0_HOT_PLUG_STS_1	BIT(29)
+#define PG5_PMA0_HOT_PLUG_STS_0	BIT(28)
+#define PG5_PMA1_HOT_PLUG_STS_3	BIT(27)
+#define PG5_PMA1_HOT_PLUG_STS_2	BIT(26)
+#define PG5_PMA1_HOT_PLUG_STS_1	BIT(25)
+#define PG5_PMA1_HOT_PLUG_STS_0	BIT(24)
+#define TC_TBT1_HOT_PLUG_STS	BIT(13)
+#define TC_TBT0_HOT_PLUG_STS	BIT(12)
+#define TC_PCIE3_HOT_PLUG_STS	BIT(11)
+#define TC_PCIE2_HOT_PLUG_STS	BIT(10)
+#define TC_PCIE1_HOT_PLUG_STS	BIT(9)
+#define TC_PCIE0_HOT_PLUG_STS	BIT(8)
+#define IOE_HOT_PLUG_STS	BIT(7)
+#define SPB_HOT_PLUG_STS	BIT(1)
+#define SPA_HOT_PLUG_STS	BIT(0)
+/* 0x18		GPE1_STS_95_64	General Purpose Event 1 Status [63:32] */
+#define PG5_PMA0_PCI_EXP_STS_3	BIT(31)
+#define PG5_PMA0_PCI_EXP_STS_2	BIT(30)
+#define PG5_PMA0_PCI_EXP_STS_1	BIT(29)
+#define PG5_PMA0_PCI_EXP_STS_0	BIT(28)
+#define PG5_PMA1_PCI_EXP_STS_3	BIT(27)
+#define PG5_PMA1_PCI_EXP_STS_2	BIT(26)
+#define PG5_PMA1_PCI_EXP_STS_1	BIT(25)
+#define PG5_PMA1_PCI_EXP_STS_0	BIT(24)
+#define TC_TBT1_PCI_EXP_STS	BIT(13)
+#define TC_TBT0_PCI_EXP_STS	BIT(12)
+#define TC_PCIE3_PCI_EXP_STS	BIT(11)
+#define TC_PCIE2_PCI_EXP_STS	BIT(10)
+#define TC_PCIE1_PCI_EXP_STS	BIT(9)
+#define TC_PCIE0_PCI_EXP_STS	BIT(8)
+#define IOE_PCI_EXP_STS		BIT(7)
+#define SPB_PCI_EXP_STS		BIT(1)
+#define SPA_PCI_EXP_STS		BIT(0)
+/* 0x1C		GPE1_EN_31_0	General Purpose Event 1 Enable [31:0] */
+#define CNVI_BT_PME_B0_EN	BIT(18)
+#define TC_IOM_PME_B0_EN	BIT(17)
+#define TC_TBT1_PME_B0_EN	BIT(16)
+#define TC_TBT0_PME_B0_EN	BIT(15)
+#define LPSS_PME_B0_EN		BIT(14)
+#define CSE_PME_B0_EN		BIT(13)
+#define XDCI_PME_B0_EN		BIT(12)
+#define ACE_PME_B0_EN		BIT(10)
+#define XHCI_PME_B0_EN		BIT(9)
+#define SATA_PME_B0_EN		BIT(8)
+#define CSME_PME_B0_EN		BIT(7)
+#define GBE_PME_B0_EN		BIT(6)
+#define CNVI_PME_B0_EN		BIT(5)
+#define OSSE_PME_B0_EN		BIT(4)
+#define TBTLSX_PME_B0_EN	BIT(1)
+/* 0x20		GPE1_EN_63_32	General Purpose Event 1 Enable [63:32] */
+#define PG5_PMA0_HOT_PLUG_EN_3	BIT(31)
+#define PG5_PMA0_HOT_PLUG_EN_2	BIT(30)
+#define PG5_PMA0_HOT_PLUG_EN_1	BIT(29)
+#define PG5_PMA0_HOT_PLUG_EN_0	BIT(28)
+#define PG5_PMA1_HOT_PLUG_EN_3	BIT(27)
+#define PG5_PMA1_HOT_PLUG_EN_2	BIT(26)
+#define PG5_PMA1_HOT_PLUG_EN_1	BIT(25)
+#define PG5_PMA1_HOT_PLUG_EN_0	BIT(24)
+#define TC_TBT1_HOT_PLUG_EN	BIT(13)
+#define TC_TBT0_HOT_PLUG_EN	BIT(12)
+#define TC_PCIE3_HOT_PLUG_EN	BIT(11)
+#define TC_PCIE2_HOT_PLUG_EN	BIT(10)
+#define TC_PCIE1_HOT_PLUG_EN	BIT(9)
+#define TC_PCIE0_HOT_PLUG_EN	BIT(8)
+#define IOE_HOT_PLUG_EN		BIT(7)
+#define SPB_HOT_PLUG_EN		BIT(1)
+#define SPA_HOT_PLUG_EN		BIT(0)
+/* 0x24		GPE1_EN_95_64	General Purpose Event 1 Enable [63:32] */
+#define PG5_PMA0_PCI_EXP_EN_3	BIT(31)
+#define PG5_PMA0_PCI_EXP_EN_2	BIT(30)
+#define PG5_PMA0_PCI_EXP_EN_1	BIT(29)
+#define PG5_PMA0_PCI_EXP_EN_0	BIT(28)
+#define PG5_PMA1_PCI_EXP_EN_3	BIT(27)
+#define PG5_PMA1_PCI_EXP_EN_2	BIT(26)
+#define PG5_PMA1_PCI_EXP_EN_1	BIT(25)
+#define PG5_PMA1_PCI_EXP_EN_0	BIT(24)
+#define TC_TBT1_PCI_EXP_EN	BIT(13)
+#define TC_TBT0_PCI_EXP_EN	BIT(12)
+#define TC_PCIE3_PCI_EXP_EN	BIT(11)
+#define TC_PCIE2_PCI_EXP_EN	BIT(10)
+#define TC_PCIE1_PCI_EXP_EN	BIT(9)
+#define TC_PCIE0_PCI_EXP_EN	BIT(8)
+#define IOE_PCI_EXP_EN		BIT(7)
+#define SPB_PCI_EXP_EN		BIT(1)
+#define SPA_PCI_EXP_EN		BIT(0)
 
 /*
  * Enable SMI generation:
@@ -134,6 +278,10 @@ struct chipset_power_state {
 	uint16_t pm1_sts;
 	uint16_t pm1_en;
 	uint32_t pm1_cnt;
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
+	uint32_t gpe1_sts[3];
+	uint32_t gpe1_en[3];
+#endif
 	uint16_t tco1_sts;
 	uint16_t tco2_sts;
 	uint32_t gpe0_sts[4];