fix(sdio): bounce SDRAM-targeted reads through internal SRAM on H750#7318
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raphaelcoeffic wants to merge 1 commit intomainfrom
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fix(sdio): bounce SDRAM-targeted reads through internal SRAM on H750#7318raphaelcoeffic wants to merge 1 commit intomainfrom
raphaelcoeffic wants to merge 1 commit intomainfrom
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On STM32H750, DMA from SDMMC into SDRAM can cause FIFO overruns when the SDRAM controller can't keep up with the SDMMC receive rate. The disk cache fills go into internal SRAM so they're safe, but three paths bypass the cache and hand the caller's buffer (often an SDRAM heap allocation) directly to the DMA: - reads larger than DISK_CACHE_BLOCK_SECTORS (disk_cache.cpp:149) - reads near the end of the disk (disk_cache.cpp:156) - FatFs f_read multi-sector reads that exceed the block size Drop the SDRAM heap clause from _IS_DMA_BUFFER on STM32H7 so SDRAM buffers take the bounce path, and grow the bounce buffer to 8 KB (DISK_CACHE_BLOCK_SECTORS) on H7 to keep throughput reasonable for large reads. H7RS keeps the original behaviour — its SDRAM is fast enough not to trigger this.
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@sneone can you please test with this if that improves anything? |
Contributor
Ok, I tested it and it works fine. I even changed the SD card clock to 50M and it still reads and writes to the SD card correctly (I only did a few dozen simple tests). I think it would be better to change the variable scratch to 32-byte alignment. |
Member
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This should be able to merge in 2.11 branch, right? |
Member
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I'll try to cherry-pick it in, will see how that goes. @raphaelcoeffic Don't forget to consider this from above
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Member
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I tried to cherry pick to 2.11, no conflicts |
Member
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On STM32H750, DMA from SDMMC into SDRAM can cause FIFO overruns when the SDRAM controller can't keep up with the SDMMC receive rate. The disk cache fills go into internal SRAM so they're safe, but three paths bypass the cache and hand the caller's buffer (often an SDRAM heap allocation) directly to the DMA:
Drop the SDRAM heap clause from _IS_DMA_BUFFER on STM32H7 so SDRAM buffers take the bounce path, and grow the bounce buffer to 8 KB (DISK_CACHE_BLOCK_SECTORS) on H7 to keep throughput reasonable for large reads. H7RS keeps the original behaviour — its SDRAM is fast enough not to trigger this.