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Missing raw_dims parameter in Module.Reg Class

Status: Open.

#66 In PyHDI/veriloggen;

· RuxueJ opened on Oct 7, 2025

Which standard does this package follow?

Status: Open.

#65 In PyHDI/veriloggen;

· BlingBlingKing opened on May 13, 2025

Please add support for VerilogA

Status: Open.

#64 In PyHDI/veriloggen;

· mwolodzk opened on Apr 2, 2025

License does not have year or author clause

Status: Open.

#63 In PyHDI/veriloggen;

· lemoncmd opened on Sep 16, 2024

Jupyter notebook 'hello_led.ipynb'

Status: Open.

#62 In PyHDI/veriloggen;

· zehonyi21 opened on Aug 9, 2024

Java runtime error

Status: Open.

#61 In PyHDI/veriloggen;

· VPIgnite99 opened on Feb 21, 2024

# The task call part in veriloggen library is not generated correctly

Status: Open.

#60 In PyHDI/veriloggen;

· Hikakkun opened on Jan 24, 2024

read_verilog_module does not support instances with unconnected ports, will generate a TypeError.

Status: Open.

#58 In PyHDI/veriloggen;

· darcy-wu opened on Aug 12, 2023

Slice in Wire with two dimension

Status: Open.

#47 In PyHDI/veriloggen;

· LucasBraganca opened on Mar 21, 2022

Creating a combinational sequence

Status: Open.

#46 In PyHDI/veriloggen;

· kiteloopdesign opened on Jun 14, 2021

to_verilog("file.v") creates two empty lines at beginning of file

Status: Open.

#44 In PyHDI/veriloggen;

· kiteloopdesign opened on May 18, 2021

Creating input with literal BW in the form of [n:0] instead of [n-1:0]

Status: Open.

#43 In PyHDI/veriloggen;

· kiteloopdesign opened on Apr 30, 2021