GitHub - RehanQasim-dev/Single-Cycle-RISCV-32I-Processor: Sytem verilog code for single cycle RISCV-32I processor.It supports all the base level instructions. · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.gitignore		.gitignore
2020-EE-162.pdf		2020-EE-162.pdf
ALU.sv		ALU.sv
Branch_block.sv		Branch_block.sv
Controller.sv		Controller.sv
Instrmem.sv		Instrmem.sv
Instrmem_dump.vcd		Instrmem_dump.vcd
LS_controller.sv		LS_controller.sv
RISC_R_dump.vcd		RISC_R_dump.vcd
RISC_V.sv		RISC_V.sv
RISC_V_tb.sv		RISC_V_tb.sv
Regfile.sv		Regfile.sv
assembly_test.txt		assembly_test.txt
data_mem.sv		data_mem.sv
data_path.sv		data_path.sv
instructions.txt		instructions.txt
mux16x1.sv		mux16x1.sv
registervalues.txt		registervalues.txt

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Sytem verilog code for single cycle RISCV-32I processor.It supports all the base level instructions.

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