[slang] Automatically blackbox macros from ADDITIONAL_LIBS#3967
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oharboe wants to merge 1 commit intoThe-OpenROAD-Project:masterfrom
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[slang] Automatically blackbox macros from ADDITIONAL_LIBS#3967oharboe wants to merge 1 commit intoThe-OpenROAD-Project:masterfrom
oharboe wants to merge 1 commit intoThe-OpenROAD-Project:masterfrom
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When using the slang HDL frontend, macros defined in ADDITIONAL_LIBS
liberty files were not automatically blackboxed. If the same module
had a competing Verilog definition in the source files, slang would
elaborate the Verilog version instead of using the liberty view.
Fix by extracting cell names from ADDITIONAL_LIBS and passing them
as --blackboxed-module arguments to slang, making the behavior
consistent with the builtin Verilog frontend.
Tested:
asap7/uart with a fake ADDITIONAL_LIBS containing uart_tx:
Confirmed slang blackboxes uart_tx from the liberty file
instead of elaborating it from the Verilog source.
asap7/cva6 (which uses slang and ADDITIONAL_LIBS with fakeram
macros that also have .sv definitions in VERILOG_FILES):
make DESIGN_CONFIG=designs/asap7/cva6/config.mk do-yosys-canonicalize
Passes in ~5s with no errors.
asap7/uart without ADDITIONAL_LIBS:
Normal synthesis still passes (no regression).
Fixes The-OpenROAD-Project#3849
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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@povik I tested Claude to see if it could fix this problem. Is this helpful?
When using the slang HDL frontend, macros defined in ADDITIONAL_LIBS liberty files were not automatically blackboxed. If the same module had a competing Verilog definition in the source files, slang would elaborate the Verilog version instead of using the liberty view.
Fix by extracting cell names from ADDITIONAL_LIBS and passing them as --blackboxed-module arguments to slang, making the behavior consistent with the builtin Verilog frontend.
Tested:
asap7/uart with a fake ADDITIONAL_LIBS containing uart_tx:
Confirmed slang blackboxes uart_tx from the liberty file
instead of elaborating it from the Verilog source.
asap7/cva6 (which uses slang and ADDITIONAL_LIBS with fakeram
macros that also have .sv definitions in VERILOG_FILES):
make DESIGN_CONFIG=designs/asap7/cva6/config.mk do-yosys-canonicalize
Passes in ~5s with no errors.
asap7/uart without ADDITIONAL_LIBS:
Normal synthesis still passes (no regression).
Fixes #3849