hcd/dwc2: fix FIFO allocation and periodic transfer

[HiFiPhile]

This pull request introduces significant improvements and bug fixes to the periodic transfer scheduling and error handling logic in the DWC2 USB host controller driver. The changes improve the accuracy and reliability of periodic (interrupt and isochronous) transfers, especially in handling missed service intervals, transfer deferral, and completion. Additionally, several code cleanups and minor enhancements have been made.

Periodic Transfer Scheduling and Deferral Improvements:

• Added new fields (periodic_phase, xfer_pending, periodic_frame) to hcd_endpoint_t to track the phase and deferral status of periodic transfers, and expanded uframe_interval and uframe_countdown to 19 bits for better interval tracking.
• Implemented logic to defer periodic transfers if the current microframe is not aligned, using new helper functions periodic_xfer_countdown and periodic_xfer_defer. Transfers are now only kicked off when the correct interval is reached. [1] [2]
• Updated SOF (Start of Frame) interrupt handler to decrement the countdown for deferred periodic transfers and only start them when ready, improving timing accuracy.

Error Handling and Completion for Missed Periodic Intervals:

• Added handling for HCINT_FARME_OVERRUN (missed frame/interval) in both IN and OUT directions for both slave and DMA modes. Isochronous endpoints now report successful completion with empty data, while interrupt endpoints retry the transfer. [1] [2] [3] [4]
• Ensured that aborting a transfer clears any pending periodic transfer state.

General Code and Logic Enhancements:

• Improved PID (Packet Identifier) management to avoid toggling for isochronous endpoints and to be more robust for other types. [1] [2] [3]
• Added HCD_FRAME_NUMBER_MASK for safer frame number calculations and masking.
• Minor improvements to endpoint open logic and FIFO size calculations for clarity and correctness. [1] [2] [3]

Interrupt Handling Adjustments:

• Refactored the main interrupt handler to ensure channel interrupts are handled after FIFO draining, preventing missed completions. [1] [2]

These changes collectively make periodic transfer scheduling more robust and reliable, particularly for isochronous and interrupt endpoints, and improve the driver's compliance with USB host controller requirements.

[github-actions]

Hardware-in-the-loop (HIL) Test Report

hfp.json

Skipped by PR selection: no affected boards on this rig.

tinyusb-esp.json

Scoped run: 2 board(s) — espressif_p4_function_ev, espressif_s3_devkitm. Boards/tests not listed were not run.

✅ 0 passed · ❌ 8 failed · ⚪ 0 skipped · blank not run

Board	msc_file_explorer_freertos	device_info	duration
espressif_p4_function_ev	❌	❌
espressif_p4_function_ev-DMA	❌	❌
espressif_s3_devkitm	❌	❌
espressif_s3_devkitm-DMA	❌	❌

tinyusb.json

Scoped run: 1 board(s) — stm32f723disco. Boards/tests not listed were not run.

✅ 7 passed · ❌ 1 failed · ⚪ 0 skipped · blank not run

Board	msc_file_explorer	msc_file_explorer_freertos	cdc_msc_hid	device_info	duration
stm32f723disco	12192 KB/s	3912 KB/s	❌	✅
stm32f723disco-DMA	14169 KB/s	3942 KB/s	✅	✅

[github-actions]

MemBrowse Memory Report

Top 10 targets by memory change (%) (out of 295 targets) View Project Dashboard →

target	.text	.rodata	.data	.bss	total	% diff
feather_stm32f405/hid_controller	21,564 → 22,192 (+628)	—	—	—	22,904 → 23,532 (+628)	+2.7%
feather_stm32f405/device_info	22,336 → 22,964 (+628)	—	—	—	23,800 → 24,428 (+628)	+2.6%
feather_stm32f405/bare_api	22,920 → 23,548 (+628)	—	—	—	24,472 → 25,100 (+628)	+2.6%
feather_stm32f405/midi_rx	23,492 → 24,120 (+628)	—	—	—	24,620 → 25,248 (+628)	+2.6%
stlinkv3mini/hid_controller	22,736 → 23,348 (+612)	—	—	—	24,204 → 24,816 (+612)	+2.5%
feather_stm32f405/midi2_host	24,004 → 24,632 (+628)	—	—	—	25,404 → 26,032 (+628)	+2.5%
stlinkv3mini/device_info	23,504 → 24,116 (+612)	—	—	—	25,096 → 25,708 (+612)	+2.4%
stlinkv3mini/bare_api	24,092 → 24,704 (+612)	—	—	—	25,772 → 26,384 (+612)	+2.4%
stlinkv3mini/midi_rx	24,676 → 25,288 (+612)	—	—	—	25,932 → 26,544 (+612)	+2.4%
stlinkv3mini/midi2_host	25,136 → 25,748 (+612)	—	—	—	26,664 → 27,276 (+612)	+2.3%

[Copilot]

Pull request overview

This PR fixes DWC2 host DFIFO layout in the Synopsys DWC2 HCD driver by ensuring the host RxFIFO remains anchored at address 0 and by correctly sizing per-host-channel reserved words using the decoded host channel count.

Changes:

• Use dwc2_channel_count() to size reserved DMA metadata space and per-channel RxFIFO status words.
• Stop subtracting rxfsiz from the top-of-DFIFO allocator (so PTX/NPTX no longer get placed at address 0 and overlap RxFIFO).

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[Copilot]

🟡 Changes recommended

hcd_edpt_abort_xfer() has a confirmed race with the SOF ISR and returns success even when no transfer is aborted, which can break abort semantics.

Once you've addressed the issues Copilot identified, you can request another Copilot review.

Review details

• Files reviewed: 1/1 changed files
• Comments generated: 1
• Review effort level: Lite

[Copilot]

🟡 Changes recommended

There are confirmed correctness issues (frame-number masking width and a race in aborting deferred periodic transfers) that can mis-schedule transfers or allow aborted transfers to still start.

Once you've addressed the issues Copilot identified, you can request another Copilot review.

Review details

Suppressed comments (1)

src/portable/synopsys/dwc2/hcd_dwc2.c:799

• Clearing xfer_pending/uframe_countdown without an interrupt-critical section can race with the SOF ISR (which decrements uframe_countdown and can kick off the transfer). This can result in abort returning true while the deferred transfer still starts.

  if (edpt->xfer_pending) {
    edpt->xfer_pending = 0;
    edpt->uframe_countdown = 0;
    return true;
  }

• Files reviewed: 1/1 changed files
• Comments generated: 1
• Review effort level: Lite