The Architecture-Project is centered around the design and implementation of a simple 5-stage pipelined processor following a RISC-like instruction set architecture (ISA). The processor is von Neumann based and consists of key components such as general-purpose registers, program counter (PC), stack pointer (SP), and memory.
- Registers: Eight 4-byte general-purpose registers (R0 to R7), a program counter (PC), and a stack pointer (SP).
- Memory: 4 KB of 16-bit word-addressable memory. The data bus width between memory and the processor is 16 bits for instruction memory and 32 bits for data memory.
- Pipeline Stages:
- Fetch
- Decode
- Execute
- Memory
- Write Back
The ISA is designed with a RISC-like approach, emphasizing simplicity and efficiency. The instruction set includes various operations, and the format of instructions is illustrated in the provided images.
The control signals used in the processor are documented in a Google Spreadsheet. This includes signals for each stage of the pipeline, enabling the control of various operations during the fetch, decode, execute, memory, and write back stages. Control Signals Spreadsheet
The schematic diagram of the processor is visualized using an online drawing tool. It provides an overview of the components and their connections in the system. Schematic Diagram
The assembler for this processor translates human-readable assembly code into machine code that the processor can execute. enabling programmers to write code at a higher level and then convert it into the binary format understandable by the processor.
To assemble your code, use the following command:
python assembler.py -i code.txt -o "output_file"
Mostafa Elsayed |
Mohamed Maher |
Aly Abdel Motaleb |
Walid Khamees |