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This PR adds the following RISCV targets to the tier 2 list of targets:
The rationale behind adding them directly to tier 2, is that the other bare metal targets already exist at tier 2, and these new targets are the same with an additional target feature enabled.
As well as the additional targets, this PR fills out the platform support document(s) that were previously missing.
The RISC-V bare metal targets don't currently have a platform support document, but this will change soon as the RISC-V team from the Rust-embedded working group will maintain these once davidtwco#1 is merged (and @davidtwco's upstream PR is merged after). For the time being you can cc myself or any other member of the RISC-V team: https://github.com/orgs/rust-embedded/teams/riscv.RISC-V is an open specification, used and accessible to anyone including individuals.
This rust-embedded working group's RISCV team will maintain these targets.
I don't forsee this being an issue, the RISCV team will ensure we avoid undue burden for the general Rust community.
There are links to resources we maintain in the re wg org in the platform support document.
Documented in the platform support document.
New target features in RISCV can drastically change the capability of a CPU, hence the need for a separate target to support different variants. We aim to support any ratified RISCV extensions.
coreis fully implemented.RISCV is a well-established and well-maintained LLVM backend. To the best of my knowledge, the backend won't cause the generated code to have undefined behaviour.
The C calling convention is supported by RISCV.
For the last 4-5 years many of these RISCV targets have been building in CI without any known issues.
Not applicable, in the future we may wish to add qemu tests but this is out of scope for now.
To the best of my knowledge, this will not induce a burden on the current CI infra.
Cross-compilation is supported and documented in the platform support document.
There are no additional license issues to worry about.
The RISCV team agrees not to do this.
The RISCV team will fix any issues in a timely manner.